FPGA Groups

FPGA Groups (http://www.fpgacentral.com/group/index.php)
-   Verilog (http://www.fpgacentral.com/group/forumdisplay.php?f=12)
-   -   Simulation of Xilinx ROcket IOs (http://www.fpgacentral.com/group/showthread.php?t=45290)

[email protected] 03-06-2006 10:57 AM

Simulation of Xilinx ROcket IOs
 
Hello All,

I want to use Xilinx v2p or v4 rocket IOs in one of my designs.
right now I am using Xilinx webpack 8.1 and modelsim se/pe.


can any body tell me that if I generate a rocket IO instance (without
8b10b and crc) as a simple serdes How do I simulate it...?


Does the Rocket IO Instance has any output pins for PLL Locked
signals...?


I am trying to simulate a transmitter by a simple test bench as to
provide reset, clock and 8-bit parallel data, but nothing is coming out

on serial tx pin.


Please guide me .
Thanks in advance.


Regards,
Kedar



All times are GMT +1. The time now is 07:43 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved