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-   -   Simulation of Xilinx ROcket IOs (http://www.fpgacentral.com/group/showthread.php?t=45290)

[email protected] 03-06-2006 10:57 AM

Simulation of Xilinx ROcket IOs
Hello All,

I want to use Xilinx v2p or v4 rocket IOs in one of my designs.
right now I am using Xilinx webpack 8.1 and modelsim se/pe.

can any body tell me that if I generate a rocket IO instance (without
8b10b and crc) as a simple serdes How do I simulate it...?

Does the Rocket IO Instance has any output pins for PLL Locked

I am trying to simulate a transmitter by a simple test bench as to
provide reset, clock and 8-bit parallel data, but nothing is coming out

on serial tx pin.

Please guide me .
Thanks in advance.


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