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Old 10-12-2006, 11:07 AM
A2500
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Default Simulation in Synopsys

Hi all,

first of all sorry for so basic question might looks a little stupid.

Please advise me " how to simulate Verilog Design before synthesis in
Synopsys" I got information about VCS but not getting a clue how to
start with it. Any kind of link or hint is appereciated.

thanks in advanec,

mirza

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Old 10-12-2006, 12:55 PM
Ajeetha
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Default Re: Simulation in Synopsys

Hi Mirza,
Do you have a "testbench" (that you don't pass to Synthesis but
only for sim), if not start doing some google search on that. For VCS,
read doc as suggested, "vcs -doc" is good start with.

Easiest is:

vcs *.v -R

The above will compile all verilog files and run simulation for you -
can't be easier than that :-)

Regards
Ajeetha, CVC
www.noveldv.com

A2500 wrote:
> Hi all,
>
> first of all sorry for so basic question might looks a little stupid.
>
> Please advise me " how to simulate Verilog Design before synthesis in
> Synopsys" I got information about VCS but not getting a clue how to
> start with it. Any kind of link or hint is appereciated.
>
> thanks in advanec,
>
> mirza


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Old 10-12-2006, 02:38 PM
Petter Gustad
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Default Re: Simulation in Synopsys

"A2500" <[email protected]> writes:

> Please advise me " how to simulate Verilog Design before synthesis in
> Synopsys" I got information about VCS but not getting a clue how to
> start with it. Any kind of link or hint is appereciated.


doc/UserGuide/vcs.pdf under your installation-directory is a good
place to start.

Petter
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