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Old 09-21-2004, 12:28 PM
FairChild
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Default Simulation problem in CVER

Hi

1) Recently i tried to do functional simualtion of my code, which uses
some Altera primitives (Altdpram), in CVER. I found that the simulator is
doing a core dump. The same is happening with Xilinx BRAM primitive. I am
not sure if these primitives are the real problem. I would like to know if
anyone else have faced the same problem or similar problem (and a way to
solve it )
FYI: I am using CVER in Cygwin environment. I tried the same code in
almost all the recent versions of CVER.

2) I also tried to do timing simulation with the altera library and then
with Xilinx library(i used compiler directive to select the primitives
before synthesis). CVER is having some problem with SDF annotation
(probably i may be having some problem) I could not get them working. I
would like to know if anybody have done timing simulation with CVER. If
yes..what is the procedure. I followed the procedure given in Quartus
handbook.

Thanks


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