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  #1 (permalink)  
Old 01-27-2010, 11:23 PM
rekz
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Default sign extension in verilog

I would like to design a 16 to 32-bit sign extension unit. I would
like to preserve the number's sign (positive/negative). So I guess
after I append digits to the MSB then I would need to take care of the
sign's, how could I do this in verilog?
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  #2 (permalink)  
Old 01-27-2010, 11:30 PM
rekz
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Default Re: sign extension in verilog

On Jan 27, 4:23*pm, rekz <[email protected]> wrote:
> I would like to design a 16 to 32-bit sign extension unit. I would
> like to preserve the number's sign (positive/negative). So I guess
> after I append digits to the MSB then I would need to take care of the
> sign's, how could I do this in verilog?


is it just as simple as this:

module SignExtension(a, result);

input [15:0] a; // 16-bit input
output [31:0] result; // 32-bit output

assign result = { 16{a[31]}, a };

endmodule
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  #3 (permalink)  
Old 01-28-2010, 12:07 AM
David Rogoff
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Default Re: sign extension in verilog

On 2010-01-27 15:30:27 -0800, rekz said:

> On Jan 27, 4:23*pm, rekz <[email protected]> wrote:
>> I would like to design a 16 to 32-bit sign extension unit. I would
>> like to preserve the number's sign (positive/negative). So I guess
>> after I append digits to the MSB then I would need to take care of the
>> sign's, how could I do this in verilog?

>
> is it just as simple as this:
>
> module SignExtension(a, result);
>
> input [15:0] a; // 16-bit input
> output [31:0] result; // 32-bit output
>
> assign result = { 16{a[31]}, a };


This should be assign result = { 16{a[15]}, a };

Basically, you just take the MSB of the input and repeat it to fill to
the left.

>
> endmodule

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  #4 (permalink)  
Old 01-28-2010, 12:36 AM
rekz
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Default Re: sign extension in verilog

On Jan 27, 5:07*pm, David Rogoff <[email protected]> wrote:
> On 2010-01-27 15:30:27 -0800, rekz said:
>
> > On Jan 27, 4:23*pm, rekz <[email protected]> wrote:
> >> I would like to design a 16 to 32-bit sign extension unit. I would
> >> like to preserve the number's sign (positive/negative). So I guess
> >> after I append digits to the MSB then I would need to take care of the
> >> sign's, how could I do this in verilog?

>
> > is it just as simple as this:

>
> > module SignExtension(a, result);

>
> > input [15:0] a; // 16-bit input
> > output [31:0] result; // 32-bit output

>
> > assign result = { 16{a[31]}, a };

>
> This should be assign result = { 16{a[15]}, a };
>
> Basically, you just take the MSB of the input and repeat it to fill to
> the left.
>
>
>
> > endmodule

>
>


And doing this will preserve the sign of the numbers?? Why?
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  #5 (permalink)  
Old 01-28-2010, 12:44 AM
Cary R.
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Default Re: sign extension in verilog

David Rogoff wrote:
> On 2010-01-27 15:30:27 -0800, rekz said:
>
>> On Jan 27, 4:23 pm, rekz <[email protected]> wrote:
>> I would like to design a 16 to 32-bit sign extension unit. I would
>> like to preserve the number's sign (positive/negative). So I guess
>> after I append digits to the MSB then I would need to take care of the
>> sign's, how could I do this in verilog?
>>
>> is it just as simple as this:
>>
>> module SignExtension(a, result);
>> input [15:0] a; // 16-bit input
>> output [31:0] result; // 32-bit output
>>
>> assign result = { 16{a[31]}, a };
>>
>> endmodule

>
> This should be assign result = { 16{a[15]}, a };
>
> Basically, you just take the MSB of the input and repeat it to fill to
> the left.


Or use a signed right expression and the tools should take care of it
for you. There can be some subtlety with this, but it does work when you
understand the rules.

Cary
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  #6 (permalink)  
Old 01-28-2010, 12:47 AM
Cary R.
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Default Re: sign extension in verilog

rekz wrote:
> On Jan 27, 5:07 pm, David Rogoff <[email protected]> wrote:
>> On 2010-01-27 15:30:27 -0800, rekz said:
>>
>>> On Jan 27, 4:23 pm, rekz <[email protected]> wrote:
>>>> I would like to design a 16 to 32-bit sign extension unit. I would
>>>> like to preserve the number's sign (positive/negative). So I guess
>>>> after I append digits to the MSB then I would need to take care of the
>>>> sign's, how could I do this in verilog?
>>> is it just as simple as this:
>>> module SignExtension(a, result);
>>> input [15:0] a; // 16-bit input
>>> output [31:0] result; // 32-bit output
>>> assign result = { 16{a[31]}, a };

>> This should be assign result = { 16{a[15]}, a };
>>
>> Basically, you just take the MSB of the input and repeat it to fill to
>> the left.
>>
>>
>>
>>> endmodule

>>

>
> And doing this will preserve the sign of the numbers?? Why?


Read up on twos-complement numbers!

Cary
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  #7 (permalink)  
Old 01-28-2010, 11:11 AM
Jonathan Bromley
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Default Re: sign extension in verilog

On Wed, 27 Jan 2010 16:44:28 -0800, "Cary R." wrote:

>> Basically, you just take the MSB of the input and
>> repeat it to fill to the left.

>
>Or use a signed right expression and the tools should take
>care of it for you. There can be some subtlety with this,


Nominated for Understatement Of The Year.

> but it does work when you understand the rules.


And spectacularly and mysteriously fails to work when you
don't, or when you do understand but you forget one of
the many Gotchas.

I would very strongly urge beginners to steer clear of
Verilog signed arithmetic - especially beginners like
the OP whose grasp of twos-complement seems shaky :-)
--
Jonathan Bromley
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  #8 (permalink)  
Old 01-28-2010, 03:23 PM
Jan Decaluwe
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Default Re: sign extension in verilog

Jonathan Bromley wrote:
> On Wed, 27 Jan 2010 16:44:28 -0800, "Cary R." wrote:
>
>>> Basically, you just take the MSB of the input and
>>> repeat it to fill to the left.

>> Or use a signed right expression and the tools should take
>> care of it for you. There can be some subtlety with this,

>
> Nominated for Understatement Of The Year.
>
>> but it does work when you understand the rules.

>
> And spectacularly and mysteriously fails to work when you
> don't, or when you do understand but you forget one of
> the many Gotchas.
>
> I would very strongly urge beginners to steer clear of
> Verilog signed arithmetic - especially beginners like
> the OP whose grasp of twos-complement seems shaky :-)


Correct advice, but now those poor beginners must be
really confused :-) They might intuitively think that
handling negative integers is a common task that should
be simple.

My advice to them: think outside the box for a while,
before attempting to become a Verilog guru. Perhaps your
intuition is right, and it's the HDL language designers
that have it all wrong. Perhaps there is a better way.

To start thinking outside the box, read this:

http://www.jandecaluwe.com/hdldesign/counting.html

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
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  #9 (permalink)  
Old 01-28-2010, 06:23 PM
Cary R.
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Default Re: sign extension in verilog

Jonathan Bromley wrote:

> And spectacularly and mysteriously fails to work when you
> don't, or when you do understand but you forget one of
> the many Gotchas.


Been there seen that, but sometime not using it is even more painful.
For example in my current design I have a signed signal that represents
a correction value as 0.2dB per step. This needs to be expanded to
0.15dB per step with the correct rounding. Then because of a mistake in
the polarity of the analog system I need to negate the result. With
signed registers and arithmetic this isn't too bad to look at and
understand. Well the rounding of negative values is a bit complicated,
but that's completely independent and I added ample comments. ;-)

> I would very strongly urge beginners to steer clear of
> Verilog signed arithmetic - especially beginners like
> the OP whose grasp of twos-complement seems shaky :-)


I won't disagree with this, but they need to understand that
alternatives exist. Otherwise they won't understand perfectly valid and
working code.

Cary
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  #10 (permalink)  
Old 01-28-2010, 06:33 PM
Cary R.
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Default Re: sign extension in verilog

rekz wrote:

> assign result = { 16{a[31]}, a };


As a side note this is invalid replication syntax. This should be
written as.

assign result = { {16{a[31]}}, a };

Notice the replication is enclosed in {}. cver does accept this invalid
syntax, but don't count on it being portable.

Cary
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