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  #1 (permalink)  
Old 05-24-2006, 11:10 PM
Guest
 
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Default Shift register implementation

Hi,

What happens with the values of register sb in the following piece of
code:
:
:
reg [3:0]sb;

always @ (posedge sclk or posedge rst)
if (rst) begin
sb[3:1] <= 0;
end
else if (pll_lock) begin
sb[3:1] <= sb[3:0];
end
:
:
always @ (posedge sclk90 or posedge rst)
if (rst) begin
sb[0] <= 0;
else if (pll_lock) begin
sb[0] <= s_in;
end
:
:
In my opinion the vector at the left side of the assignment is 3 bit
wide, and the one at the right side 4 bit....

Any ideas??

thanks,

Luc

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  #2 (permalink)  
Old 05-25-2006, 09:14 AM
Guest
 
Posts: n/a
Default Re: Shift register implementation

Thats right. Its important to visualize the design that you are
coding.

[email protected] wrote:
> Hi,
>
> What happens with the values of register sb in the following piece of
> code:
> :
> :
> reg [3:0]sb;
>
> always @ (posedge sclk or posedge rst)
> if (rst) begin
> sb[3:1] <= 0;

sb[3:0] <= 4'd0;

> end
> else if (pll_lock) begin
> sb[3:1] <= sb[3:0];

sb[3:1] <= sb[2:0];
> end
> :
> :
> always @ (posedge sclk90 or posedge rst)
> if (rst) begin
> sb[0] <= 0;
> else if (pll_lock) begin
> sb[0] <= s_in;
> end
> :
> :
> In my opinion the vector at the left side of the assignment is 3 bit
> wide, and the one at the right side 4 bit....
>
> Any ideas??
>
> thanks,
>
> Luc


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  #3 (permalink)  
Old 05-25-2006, 02:23 PM
Jason Rosinski
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Posts: n/a
Default Re: Shift register implementation

The MSB portion of this shift will just be truncated.

[email protected] wrote:
> Hi,
>
> What happens with the values of register sb in the following piece of
> code:
> :
> :
> reg [3:0]sb;
>
> always @ (posedge sclk or posedge rst)
> if (rst) begin
> sb[3:1] <= 0;
> end
> else if (pll_lock) begin
> sb[3:1] <= sb[3:0];
> end
> :
> :
> always @ (posedge sclk90 or posedge rst)
> if (rst) begin
> sb[0] <= 0;
> else if (pll_lock) begin
> sb[0] <= s_in;
> end
> :
> :
> In my opinion the vector at the left side of the assignment is 3 bit
> wide, and the one at the right side 4 bit....
>
> Any ideas??
>
> thanks,
>
> Luc
>

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  #4 (permalink)  
Old 05-26-2006, 04:47 AM
Jeremy Ralph
Guest
 
Posts: n/a
Default Re: Shift register implementation


[email protected] wrote:
> Thats right. Its important to visualize the design that you are
> coding.


Drawing waveforms, pipeline stages, and block/cloud diagrams of
sequential/combinational logic can be helpful too, especially for more
complex circuits. This also makes for good documentation.

Regarding your code, why the two clocks (i.e. sclk and sclk90)? Could
you synchronize s_in to the sclk and do something like the following?

<code lang="verilog">

reg [3:0]sb;

always @ (posedge sclk or posedge rst)
if (rst) sb <= 0;
else if (pll_lock) sb <= {sb[2:0],s_in} ;

</code>

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

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