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Old 05-15-2006, 02:54 PM
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Default Read a reg value from the outer module without declaring port

hi all....
Can i read a variable in the inner module from the outer module?.
without declare it as a out port.
regards
subin

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Old 05-15-2006, 07:09 PM
Jeremy Ralph
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Default Re: Read a reg value from the outer module without declaring port

Unfortunately, to the best of my knowledge, VHDL doesn't allow you to
sniff signals that are buried within a hierarchy, like Verilog does.
Your simulator should allow you to probe and force such values though.

VHDL does however allow global signals which can be useful for
verification purposes. To create a global signal create a package with
a signal definition in it. Then you will have access to the signal
from wherever you include the package.

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

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Old 05-15-2006, 07:21 PM
Jeremy Ralph
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Default Re: Read a reg value from the outer module without declaring port

Ooops... this is the comp.lang.verilog not comp.lang.vhdl as my
previous message assumed.

Verilog does allow you to access internals using 'hierarchical
referencing'. For example:

always @(topmodule.innermodule.regname)
$display("reg value is %0d", topmodule.innermodule.regname);

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Old 05-18-2006, 08:19 AM
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Default Re: Read a reg value from the outer module without declaring port

Thanks Jeremy Ralph...

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