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Old 04-01-2004, 12:39 AM
Steven Sharp
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Default Re: Working of continous assignment statement

"Marty" <[email protected]_nospam.net> wrote in message news:<[email protected]>...
>
> Is it true that pure transport delay can only be modeled in an always block
> with non-blocking assignments?


That is the only way I know of modeling pure transport delay.

But I don't know why someone would deliberately want pure transport
delay. If you have different propagation delays (e.g. different rise
and fall delays), pure transport can result in behavior that is
completely wrong for hardware. The output may not end up with the
last value assigned to it, and therefore may not end up consistent
with the inputs.

For realistic behavior, you would want transport delay, not pure
transport. You should be able to get that with Verilog path
delays. By default, they filter pulse widths the same way as
inertial, but you can control the pulse width filtering. If you
set it to zero, you should get transport delay.
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