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Old 06-26-2003, 07:56 PM
Asher C. Martin
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Default Re: The Verilog PLL model?

[email protected] (walter) wrote in message news:<[email protected] om>...
> Hi,
>
> Is there is any Verilog model for PLL?
> I tried the google search.
> But they are not really related to what I need.


Hi,

Altera has a FREE PLL model available when you install the Quaruts II
Web Edition Software.

https://www.altera.com/support/softw...jsp?xy=qw1_wdl

Go to the /quartus/eda/sim_lib/ dir and type "grep pll *.v"

Take care,
>Asher<

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Old 06-28-2003, 06:21 AM
Ashraf
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Default Re: The Verilog PLL model?

[email protected] (Asher C. Martin) wrote in message news:<[email protected] com>...
> [email protected] (walter) wrote in message news:<[email protected] om>...
> > Hi,
> >
> > Is there is any Verilog model for PLL?
> > I tried the google search.
> > But they are not really related to what I need.

>
> Hi,
>
> Altera has a FREE PLL model available when you install the Quaruts II
> Web Edition Software.
>
> https://www.altera.com/support/softw...jsp?xy=qw1_wdl
>
> Go to the /quartus/eda/sim_lib/ dir and type "grep pll *.v"
>
> Take care,

Hi,

There is an article which highlights the approach when I developed this model
while I was working for a Silicon vendor. I can't share you all the details
(company proprietary information), but you can pick up the idea from the
IEEE CICC proceedings 1997 Page 15.6.1-15.6.4.
This is full functional PLL model which mimics the functionality of Lockup
sequence, frequency synthesis and selection of loop filter parameters and their
affect on lock time etc etc.

Good Luck,

Ashraf
> >Asher<

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