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Old 07-16-2003, 05:32 PM
Peter Mash
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Default Re: Verilog Module won't instantiate in Xilinx ECS

Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Regards

PETER MASH


"Peter Mash" <[email protected]> wrote in message
news:[email protected]
> Dear people,
>
> I create a module, for example, a simple adder in Verilog. It synthesises
> fine. I then create a schematic symbol from it, but the ".sym" file

contains
> very little information, and when I place it in to a schematic module in

the
> project, no symbol appears.
>
> Has anybody else had the same problem? I am using the latest ISE (5.2 with
> SP 3) as part of the WebPack.
>
> Regards to all
>
> PETE MASH
>
>
>



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  #2 (permalink)  
Old 07-17-2003, 07:23 AM
Peter Mash
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Default Re: Verilog Module won't instantiate in Xilinx ECS

Yes,
e.g.

module Adder(in1,in2,out);

input wire [7:0] in1;
input wire [7:0] in2;
output wire [8:0] out;

assign out = in1 + in2;


endmodule


"Steven Sharp" <[email protected]> wrote in message
news:[email protected] om...
> "Peter Mash" <[email protected]> wrote in message

news:<[email protected]>...
> > Answer found:
> >
> > It's because the schematic symbol generator doesn't support Verilog 2001

>
> Out of curiosity, what Verilog-2001 feature were you using?
>
> Since you said it was a simple module, I am guessing ANSI-C-style
> module declarations.



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