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Old 06-28-2003, 06:21 AM
DSLuser
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Default Re: verilog instance name length

WJ wrote:
> I am tring to do back-annotation by Verilog, and encounter a problem
> as following:
> since the instance name is too long, up to 25 characters for a single
> instance name, PrimeTime generated the sdf base on the those long
> instance names, but looks Verilog-XL can take only up to 24 charaters
> as instance names, the last charater is automatically truncted in this
> case. I dumped the waveform to confirm this Verilog-XL instance name
> trunction, and also double confirm this problem by modify the sdf
> file.
> Anybody know how to solve this problem? Is there any option in
> Verilog-XL for taking long instance name? Thanks in advance!


I think Verilog-XL is nearing 'end-of-life' development status.
Although Cadence officially still provides support for the Verilog-XL
product, I don't think they are not updating it anymore. For example,
Verilog-XL supports very few IEEE 1364 Verilog-2001 syntax.

Since you can't change Verilog-XL's behavior, you have two choices:

1) use a different verilog simulator (Cadence NC-verilog,
Mentor Modeltech VSIM, Synopsys VCS are all good choices)
2) modify your netlist (like you did), to limit the length
of instance names. If you're really good with PERL, you
could handwrite a script to do something like this.

Finally, why are your instance names so long? Are you using
parameterized instances? If so, you may want to give your
RTL-synthesis 'hints' before elaboration. I think there is a
way to do this in Synopsys Design Compiler (if that's what you're
using.) You tell Design Compiler specific instances to build
(you tell it to build different versions of the parameterized
instance...you manually specify the parameter values.) Then,
when the parameterized instances are later used in other
modules, Design_Compiler automatically looks in its 'library',
and pulls your hand-specified version. I think this will
shorten the instance names, but I never tried it.

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