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Old 07-29-2003, 06:36 PM
VhdlCohen
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Default Re: Verilog-2001 parameter declarations

>I'm trying to use Verilog-2001 style module port declarations and have
>a parameter defined as well. See my example:
>
>
>module my_module (
> output [WIDTH-1:0] my_output,
> input [WIDTH-1:0] my_input
>)
>
>parameter WIDTH = 1;
>
>assign my_output = my_input;
>
>endmodule
>
>
>I can't figure out where to put the parameter declaration to get rid
>of the syntax errors that are being reported (using VCS 7.0). Can
>parameters be declared when defining ports in this manner?
>
>Thanks,
>Mark
>

Here's how:
module my_module
#(parameter WIDTH = 8) // 0 -> full board, 1 -> 1 mem unit
(
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
);

assign my_output = my_input;

endmodule // my_module

// For instantiation:
my_module
#(.WIDTH (8))
my_module1
( // output
.my_output (data_out[7:0]),
.my_input (data_in[7:0])
);
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ [email protected]
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

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