FPGA Central

> Jan Decaluwe wrote:
>>> clked : process(clk)
>>> variable cnt_v : count_t;
>>> begin
>>> if rising_edge(clk) then
>>> cnt_v := cnt_v + 1; -- increment on rising edge
>>> end if;
>>> cnt <= cnt_v; -- wire assignment outside of clocked clause
>>> end process clked;
>>
>> I never used this template, but started to think about it because
>> of my work on MyHDL.
>>
>> The question I have is: is there an equivalent (also synthesizable)
>> version for Verilog? At first sight, I don't think so, but perhaps
>> I'm wrong.

Mike Treseler wrote:

I can get the same register init, update, output
in one always block by doing something like this:

http://home.comcast.net/~mike_treseler/dup_reg_remove.v

The Quartus synthesis report and tech viewer get
the correct number of registers (5)

http://home.comcast.net/~mike_tresel...emove_tech.pdf

But I couldn't use my vhdl-style port assignment
trick to eliminate duplication in the verific RTL front end.

The verilog block uses no IF statement for the rising edge of the clock.
The rtl schematic shows 4 duplicated regs that do not
appear in the utilization report or tech schematic.

http://home.comcast.net/~mike_tresel...remove_rtl.pdf

This is really just a cosmetic problem since everything
after synthesis gets it right. The RTL schematic is generated
after analysis and rtl elaboration, but before fitting.
See http://www.verific.com/ for more information.

-- Mike Treseler