FPGA Central

[email protected] (Dave Ardrey) wrote in message news:<[email protected]. com>...
> I'm trying to set a path delay in my verilog module like so:
>
> (posedge CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
>
>
> However, when I try to simulate with VerilogXL I get the following
> error:
>
> Error! Outputs for edge-sensitive paths have to be
>
> associated with data source
> [Verilog-OESDS]
>
> "RA1SD.new", 544: (posedge CLK=>Q[15]) = 1, 1,
>
> 0.5, 1, 0.5, 1;
> 1 error
>


>
> I've seen a line exactly like the one I have in the VerilogXL
> reference guide. Any ideas what's going on here?
>
> Thanks!

Hello Dave,

You have to choose.
simple path...

(CLK => Q[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);

or edge-sensitive path :
(posedge CLK => (Q[15] +: I))=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
where I is your input.
VerilogXL expected the second one.

Marcin