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Old 07-25-2003, 11:13 PM
Steven Sharp
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Default Re: Strange construct from bug reports

Stephen Williams <[email protected]> wrote in message news:<[email protected]>...
>
> Notice the continuous assign of Q_int back to itself. The original
> reporter claimed that this sort of thing is legal.


Sure, why wouldn't it be?

> but it sure looks weird. What, for example, do the big money
> tools do with this?


We do what the Verilog source says to do: We put in a continuous
assignment which reads the value of Q_int and drives it onto its
output (which is Q_int) with the specified strength. If you want
to talk internals, it reads the final resolved value of Q_int and
drive it onto its output (which is one of the drivers that
contributes to the resolved value of Q_int) with the specified
strength. This is just what you should expect: all readers read
the final resolved value, and all drivers drive their individual
contribution to the final resolved value. That doesn't change
just because one continuous assignment is both a reader and a
driver of the same net.

It is certainly legal, and shouldn't even require any special
handling. It is even potentially useful.

I have never seen this done with a continuous assignment. However,
I have seen it done with buf gates with weak strength or the
equivalent built with two cascaded inverters built with rmos
switches. Apparently this is a common way of implementing
a transparent latch in CMOS. When the bufif isn't driving,
the weak buffer provides the feedback loop to hold the value.
When the bufif is driving, it is strong enough to override
the feedback value and put a new value into the feedback
loop.
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Old 07-26-2003, 12:37 AM
Stephen Williams
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Default Re: Strange construct from bug reports

Steven Sharp wrote:
> Stephen Williams <[email protected]> wrote in message news:<[email protected]>...
>
>>Notice the continuous assign of Q_int back to itself. The original
>>reporter claimed that this sort of thing is legal.


> Sure, why wouldn't it be?


>>but it sure looks weird. What, for example, do the big money
>>tools do with this?


> We do what the Verilog source says to do: We put in a continuous
> assignment which reads the value of Q_int and drives it onto its
> output (which is Q_int) with the specified strength. If you want
> to talk internals, it reads the final resolved value of Q_int and
> drive it onto its output (which is one of the drivers that
> contributes to the resolved value of Q_int) with the specified
> strength.


OK, you're taunting me:-(

But it finally got through my thick skull. Icarus Verilog tries
to elide useless buffers and expressions when it can, and may have
gotten carried away here.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

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Re: Strange construct from bug reports Stephen Williams Verilog 0 07-25-2003 07:36 PM


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