FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-25-2003, 06:36 PM
Stephen Williams
Posts: n/a
Default Re: Strange construct from bug reports

Avrum wrote:
> Don't confuse "legal" with "synthesizable".

I know the difference between legal syntax, simulatable constructs
and synthesizeable constructs thankyouverymuch. I'm a compiler writer,
and I was hoping some of the other compiler "geeks" that lurk these
parts would take a stab at this. The standard certainly doesn't.

> assign (pull0, pull1) q_int = q_int;
> The weak feedback drivers are then overridden by a stronger driver when the
> latch enable is enabled (which would be the bufif1).

An implicit driver (bufz in the case of Icarus Verilog) would do
that job. In those terms, this almost makes sense. These sorts
of things are the kind of headaches that really freak out compiler
writers. Users are better at finding the dark corners of a tool
then the most random of monkeys;-)

> For reference, a "better" way of describing this module
> module dont_shoot_me (Q,D,G)
> output Q;
> input D,G;
> reg Q;
> always @(G or D)
> begin
> if (G)
> Q <= D;
> end
> endmodule

This is certainly better style. Anybody following this thread should
always use this latter form for latches. The previous construct was
from a bug report. But it doesn't matter if it's weird or even stupid.
If it has well defined behavior, I have to get it right.

Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

All times are GMT +1. The time now is 05:03 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved