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Old 07-08-2003, 07:45 PM
Avrum
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Default Re: Selecting wire or trireg at runtime

What is it you are trying to do, prevent VCS from "re-compiling" or
maintaining two different versions of the source code.

If you are trying not to modify the source code, then you can use your
`ifdef, and change the behaviour of the simulation from the command line;
you define the USE_TRIREG_BUS macro from the command line by adding

+define+USE_TRIREG_BUS

to the command line when you compile the source code.

However, changing this macro (even from the command line), DOES result in an
effective change to the code (from the VCS compiler's point of view), and
hence will result in the recompilation of the code, and a new executable.

You can also probable model the behaviour of the trireg without an actual
trireg. The trireg is the equivalent to a keeper cell. If all the "other"
drivers of the net are strong drivers, then you can do something like this
(I haven't tested this...)

reg [15:0] fake_driver;

assign (weak1, weak0) my_bus = fake_driver;

initial fake_driver = 16'bzzzz_zzzz_zzzz_zzzz;

always @(my_bus)
fake_driver = my_bus;

I THINK this might work. Then you could modify this to be conditional

always @(my_bus or use_trireg_bus)
if (use_trireg_bus)
fake_driver=my_bus;
else
fake_driver = 16'bzzzz_zzzz_zzzz_zzzz; // to avoid startup problems...

(and use the testplusargs you described below)

Avrum

"Dale Bertrand" <[email protected]> wrote in message
news:[email protected] om...
> I need to model a bus in my system as a "trireg" or "wire" depending
> on the test that is running.
>
> The trireg bus models a capacitive bus that holds its previous value
> when not driven.
>
> My current solution is to use a `define to choose the type of bus:
>
> `ifdef USE_TRIREG_BUS
> trireg [15:0] my_bus;
> `else
> wire [15:0] my_bus;
> `endif
>
> Unfortunately, this solution requires me to compile multiple versions
> of the simulator (using VCS7.0). I need to choose a trireg or wire
> bus at runtime. The type of bus will not change during the
> simulation. I would like to compile one simlator and pass a plusarg
> (like +use_trireg_bus) instead of a `define to determine the type of
> bus to use.
>
> This is the best that I could come up with. Unfortunately, this
> solution generates bus contflicts on my_bus.
>
> reg use_trireg_bus;
>
> initial begin
> if ($test$plusargs("use_trireg_bus"))
> use_trireg_bus = 1;
> else
> use_trireg_bus = 0;
> end
>
> wire [15:0] my_bus;
> trireg [15:0] my_bus_stub;
> tranif1 my_bus_trans[15:0] (my_bus_stub[15:0], my_bus[15:0],
> use_trireg_bus);
>
> Does anyone know how to implement this properly in Verilog?
>
> - Dale



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