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Old 06-28-2003, 05:39 PM
Ajeetha Kumari
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Default Re: Operator Overloading in Verilog

Hi tze,
NO, as such Verilog doesn't have user defined data types and hence
I guess this was not thought about either. Can you elaborate more on
which scenario would you need this? Perhaps there is an alternate
solution (I remember reading something similar in Deepchip.com's
archive, but related to $finish and specific to VCS).


Tze Yi Yeoh <[email protected]> wrote in message news:<[email protected]>...
> Does anyone out there know if Verilog supports operator overloading like
> in VHDL? If so, can someone point me to an example?
> thanks!
> tze

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