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Old 06-27-2003, 10:44 AM
Jonathan Bromley
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Default Re: Operator Overloading in Verilog

On Thu, 26 Jun 2003 16:53:12 -0700, Tze Yi Yeoh
<[email protected]> wrote:

>Does anyone out there know if Verilog supports operator overloading like
>in VHDL? If so, can someone point me to an example?


No, it doesn't.

SystemVerilog 3.1 will offer classes, but AFAIK still no operator
overloading.

Jonathan Bromley
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