FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-13-2004, 05:35 PM
Tom Hawkins
Guest
 
Posts: n/a
Default Re: One issue about free hardware

[email protected] (Jon Beniston) wrote in message news:<[email protected] com>...
> > With two clocks and two write ports!?

>
> Ok, maybe not that particular case, but most other configurations of
> dual-port RAM can be infered. In Verilog at least, isn't this a
> problem with the language rather than the FPGA tools (i.e. you can't
> write to the same variable from two different processes)?


Verilog does not have this restriction. I've searched the LRM and
I've run testcases through two reputable implementations without
complaints (ncverilog, icarus).

Hence my frustration. We can precisely describe a dual port block-ram
in Verilog, yet the tools draw a blank. We can even preset RAMs with
values, but most, if not all, completely disregard initial statements.

Given the size of their development staff and the prices they are able
to charge, how can they still ignore important parts of the language
standard?

-Tom


>
> > Open-source doesn't *have* to mean no-cost...

>
> Sure. I was more refering to that fact that due to the quality & size
> of some open source/free software projects, the bar has been raised
> significantly.
>
> Cheers,
> JonB

Reply With Quote
  #2 (permalink)  
Old 05-14-2004, 10:45 AM
Martin Thompson
Guest
 
Posts: n/a
Default Re: One issue about free hardware

[email protected] (Tom Hawkins) writes:

> [email protected] (Jon Beniston) wrote in message news:<[email protected] com>...
> > > With two clocks and two write ports!?

> >
> > Ok, maybe not that particular case, but most other configurations of
> > dual-port RAM can be infered. In Verilog at least, isn't this a
> > problem with the language rather than the FPGA tools (i.e. you can't
> > write to the same variable from two different processes)?

>
> Verilog does not have this restriction. I've searched the LRM and
> I've run testcases through two reputable implementations without
> complaints (ncverilog, icarus).
>
> Hence my frustration. We can precisely describe a dual port block-ram
> in Verilog, yet the tools draw a blank. We can even preset RAMs with
> values, but most, if not all, completely disregard initial statements.
>


I've asked Synplify, and they can infer two-read, one-write, two-clock
RAMs currently. They plan to support the full two port functionality
in future...

Initials are another thing though!

Cheers,
Martin

--
[email protected]
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Reply With Quote
  #3 (permalink)  
Old 05-14-2004, 10:56 AM
Jon Beniston
Guest
 
Posts: n/a
Default Re: One issue about free hardware

> > Ok, maybe not that particular case, but most other configurations of
> > dual-port RAM can be infered. In Verilog at least, isn't this a
> > problem with the language rather than the FPGA tools (i.e. you can't
> > write to the same variable from two different processes)?

>
> Verilog does not have this restriction. I've searched the LRM and
> I've run testcases through two reputable implementations without
> complaints (ncverilog, icarus).


You are correct. Although it is only ever supported for simulation. I
can kind of understand why though. Take the following:

module test(c1, c2, a, b, d);
input c1, c2, a, b;
output d;
reg d;
always @(posedge c1)
d <= a;
always @(posedge c2)
d <= b;
endmodule

What logic would you synthesize it to? Have you tried this with a
behavioural synthesis tool? Maybe that could do a better job.

> Hence my frustration. We can precisely describe a dual port block-ram
> in Verilog, yet the tools draw a blank. We can even preset RAMs with
> values, but most, if not all, completely disregard initial statements.


Isn't this fixed in v200x? I do agree it's all a bit crap.

Cheers,
JonB
Reply With Quote
  #4 (permalink)  
Old 05-15-2004, 03:17 AM
john jakson
Guest
 
Posts: n/a
Default Re: One issue about free hardware

[email protected] (Jon Beniston) wrote in message news:<[email protected] com>...
> > > Ok, maybe not that particular case, but most other configurations of
> > > dual-port RAM can be infered. In Verilog at least, isn't this a
> > > problem with the language rather than the FPGA tools (i.e. you can't
> > > write to the same variable from two different processes)?

> >
> > Verilog does not have this restriction. I've searched the LRM and
> > I've run testcases through two reputable implementations without
> > complaints (ncverilog, icarus).

>
> You are correct. Although it is only ever supported for simulation. I
> can kind of understand why though. Take the following:
>
> module test(c1, c2, a, b, d);
> input c1, c2, a, b;
> output d;
> reg d;
> always @(posedge c1)
> d <= a;
> always @(posedge c2)
> d <= b;
> endmodule
>
> What logic would you synthesize it to? Have you tried this with a
> behavioural synthesis tool? Maybe that could do a better job.
>
> > Hence my frustration. We can precisely describe a dual port block-ram
> > in Verilog, yet the tools draw a blank. We can even preset RAMs with
> > values, but most, if not all, completely disregard initial statements.

>
> Isn't this fixed in v200x? I do agree it's all a bit crap.
>
> Cheers,
> JonB


BRams are a very special case since most of the time the 2 address are
different so the 2 clock domains are fully independant. If the address
should be the same then the result of the 2 concurrent writes is
undefined but the user should have taken care about that. given that,
the synthesis should be able to handle it with a warning for same
addresses.

regards

johnjakson_usa_com
Reply With Quote
  #5 (permalink)  
Old 05-15-2004, 12:05 PM
Jon Beniston
Guest
 
Posts: n/a
Default Re: One issue about free hardware

[email protected] (john jakson) wrote in message news:<[email protected] com>...
> [email protected] (Jon Beniston) wrote in message news:<[email protected] com>...
> > > > Ok, maybe not that particular case, but most other configurations of
> > > > dual-port RAM can be infered. In Verilog at least, isn't this a
> > > > problem with the language rather than the FPGA tools (i.e. you can't
> > > > write to the same variable from two different processes)?
> > >
> > > Verilog does not have this restriction. I've searched the LRM and
> > > I've run testcases through two reputable implementations without
> > > complaints (ncverilog, icarus).

> >
> > You are correct. Although it is only ever supported for simulation. I
> > can kind of understand why though. Take the following:
> >
> > module test(c1, c2, a, b, d);
> > input c1, c2, a, b;
> > output d;
> > reg d;
> > always @(posedge c1)
> > d <= a;
> > always @(posedge c2)
> > d <= b;
> > endmodule
> >
> > What logic would you synthesize it to? Have you tried this with a
> > behavioural synthesis tool? Maybe that could do a better job.
> >
> > > Hence my frustration. We can precisely describe a dual port block-ram
> > > in Verilog, yet the tools draw a blank. We can even preset RAMs with
> > > values, but most, if not all, completely disregard initial statements.

> >
> > Isn't this fixed in v200x? I do agree it's all a bit crap.
> >
> > Cheers,
> > JonB

>
> BRams are a very special case since most of the time the 2 address are
> different so the 2 clock domains are fully independant. If the address
> should be the same then the result of the 2 concurrent writes is
> undefined but the user should have taken care about that. given that,
> the synthesis should be able to handle it with a warning for same
> addresses.


Sure, but it seemed like the OP was suggesting that synthesis tools
should support everything possible in the language.

Cheers,
JonB
Reply With Quote
  #6 (permalink)  
Old 05-15-2004, 05:42 PM
Jim Lewis
Guest
 
Posts: n/a
Default Re: One issue about free hardware

Jon Beniston wrote:

>>>Ok, maybe not that particular case, but most other configurations of
>>>dual-port RAM can be infered. In Verilog at least, isn't this a
>>>problem with the language rather than the FPGA tools (i.e. you can't
>>>write to the same variable from two different processes)?

>>
>>Verilog does not have this restriction. I've searched the LRM and
>>I've run testcases through two reputable implementations without
>>complaints (ncverilog, icarus).

>
>
> You are correct. Although it is only ever supported for simulation. I
> can kind of understand why though. Take the following:
>
> module test(c1, c2, a, b, d);
> input c1, c2, a, b;
> output d;
> reg d;
> always @(posedge c1)
> d <= a;
> always @(posedge c2)
> d <= b;
> endmodule
>
> What logic would you synthesize it to? Have you tried this with a
> behavioural synthesis tool? Maybe that could do a better job.
>


Another interesting question about the proposed
code above is, during a given simulation cycle
if both clocks rise at the same time, which
executes first in simulation?

Can you re-write the code so that one always
has wins or if both happen a the same time
an 'X' is generated on d?


Cheers,
Jim
Reply With Quote
  #7 (permalink)  
Old 05-18-2004, 07:24 PM
rickman
Guest
 
Posts: n/a
Default Re: One issue about free hardware

Jim Lewis wrote:
>
> Jon Beniston wrote:
>
> >>>Ok, maybe not that particular case, but most other configurations of
> >>>dual-port RAM can be infered. In Verilog at least, isn't this a
> >>>problem with the language rather than the FPGA tools (i.e. you can't
> >>>write to the same variable from two different processes)?
> >>
> >>Verilog does not have this restriction. I've searched the LRM and
> >>I've run testcases through two reputable implementations without
> >>complaints (ncverilog, icarus).

> >
> >
> > You are correct. Although it is only ever supported for simulation. I
> > can kind of understand why though. Take the following:
> >
> > module test(c1, c2, a, b, d);
> > input c1, c2, a, b;
> > output d;
> > reg d;
> > always @(posedge c1)
> > d <= a;
> > always @(posedge c2)
> > d <= b;
> > endmodule
> >
> > What logic would you synthesize it to? Have you tried this with a
> > behavioural synthesis tool? Maybe that could do a better job.
> >

>
> Another interesting question about the proposed
> code above is, during a given simulation cycle
> if both clocks rise at the same time, which
> executes first in simulation?
>
> Can you re-write the code so that one always
> has wins or if both happen a the same time
> an 'X' is generated on d?


Same as in the real world, the result is indeterminate.

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 06:01 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved