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Old 07-29-2003, 03:20 AM
Uma Polisetti
Posts: n/a
Default Re: Negative hold times in verilog

The negative setup and hold times are an issue with smaller
geometries (especially 0.13um technolog) and the mux-D flops.
It is going to be an even bigger issue with 90nm :-(

The next issue you might face is, where the "tools" not able
to converge when the setuphold "violation" region for rise
and fall edges do not overlap. In that case, typical reaction
from the tool is to "zero out" the negative setup/hold time.
I think most of commercial tools have magic switches
to "extend" the violation region. Unfortunately, this has
penalty on simulation runtimes.

I am sorry that my explanation above "might not make sense" to
most of you. But if you have the simulator manuals, search for
"$setuphold" and "handling negative timing checks".

I can't give more details because it is Cadence's information
under NDA, but later versions of Cadence NC Verilog does very
good job on handling the rise and fall "Data" edges and different
negative setup/hold times on them.

Robert Szczygiel wrote:
> pks wrote:
> > Thank you Robert and Steven for your answers. Now I understand your
> > solutions.
> > I will try to use it. The only one problem is that I have different
> > hold times for rising/falling edge of data/clock_enable signal. I'll
> > try so manage this situation.

> As you may have noticed in the example I have given you there were two
> commands, first for the check on falling edge of the data, the second
> for the rising edge.
> >> $setuphold (posedge CK,negedge D, 180.0, -1.9,notifier,,,dCK,dD);
> >> $setuphold (posedge CK,posedge D, 218.0, -27.9,notifier,,,dCK,dD);

> Note that this two commands use the same dCK and dD wires.
> Robert
> --
> ** - Why a bike cannot stand up by itself?
> ** - Because it is two-tyred!
> -- http://2510074626/~szczygie --

Agilent Technologies Confidential

Uma Polisetti
Agilent Technologies, Inc
541-738-3335 Tel
541-738-3145 Fax
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