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Old 07-25-2003, 10:01 AM
Rajesh Bawankule
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Default Re: Loading data into memory from a file

The correct syntax is
reg [Data_Width-1:0] my_memory[0:whatever];

memory width and depth numbers have different orders.
When you specify depth the first one is the lower number and then
the higher.

Hope this helps.
Rajesh Bawankule
(Verilog FAQ: http://www.parmita.com/verilogfaq/ )

"John Vinyard" <[email protected]> wrote in message news:<[email protected]>...
> I have a memory model in verilog made with an array of registers. I'm
> trying to load data into it from a file in simulation, specifically using
> MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
> working. Any help you could give would be greatly appreciated.
>
> reg [Data_Width-1:0] memory[65535:0];
>
> Right now, I would settle for some way to execute a script from a file,
> something like:
>
> memory[0] = 36'hfeedfacea;
> memory[1]...
>
> Thanks in advance!
>
> - John

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Re: Loading data into memory from a file Steven Sharp Verilog 0 07-24-2003 10:49 PM
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