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Old 07-24-2003, 10:49 PM
Steven Sharp
Posts: n/a
Default Re: Loading data into memory from a file

"John Vinyard" <[email protected]> wrote in message news:<[email protected]>...
> I have a memory model in verilog made with an array of registers. I'm
> trying to load data into it from a file in simulation, specifically using
> MTI's Modelsim 5.7 SE. Trial and error with the $readmemh command is not
> working. Any help you could give would be greatly appreciated.

I'm not clear whether $readmemh is not working in Modelsim (which seems
unlikely), or whether you just don't have documentation for how to use it.

The syntax for the call is

$readmemh("filename", memory_name);

If you don't want to start at the lowest address and load upward from
there, you can provide an additional optional starting address argument.
You can also provide a finish address argument after that. This is
useful for getting a warning if the file failed to specify all the
elements you expected. It also allows loading in descending address
order if desired.

The syntax for the text file is hexadecimal numbers (or binary for
$readmemb), separated by white space and/or Verilog comments. The
numbers should not have a length or base format specified (which
might be your problem). So, for example, it might contain


You can also put explicit addresses into the data file, in case
you want to load specific locations in the memory without having
to specify the contents of the locations between them. This is
done with an entry of the form @1ffa (@ followed by a hex address).
Subsequent data entries will be loaded starting at that address.
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Re: Loading data into memory from a file Jim Wu Verilog 0 07-24-2003 09:39 PM
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