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Old 04-01-2004, 03:19 AM
sysv
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Default Re: About blocking timing controls

Jonathan Bromley <[email protected]> wrote in message news:<[email protected]>. ..
> On 31 Mar 2004 01:12:47 -0800, [email protected] (sysv) wrote:
>
> >We all know that delay is a kind of blocking timing control, such as:
> >#1 a = b;
> >...
> >or
> >a = #1 b;
> >...
> >
> >But I'm not sure if the 'wait' statement also is:
> >begin
> >...
> > wait(en) a = b;
> >...
> >end

>
> Yes, it is. That's why it is legal Verilog syntax to
> have no semicolon after "wait(en)". The timing control
> forms part of the associated statement.
>
> It's also possible to use wait() in intra-assignment
> timing controls:
>
> a = wait(proceed) b;
>
> and don't forget the joy of using @() as an intra-assignment
> timing control, especially in nonblocking assignment:
>
> a <= @(posedge clk) b; // sample 'b' now, but postpone
> // update of 'a' until the next posedge
>
> and even better, remember you can use repeat() as part of an
> intra-assignment delay:
>
> PipeOut <= repeat(5) @(posedge clk) PipeIn;
>
> For extra credit, explain why this is silly:
>
> Delayed <= repeat(5) wait(proceed) Input;
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
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>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Thanks a lot!!!
So can we say that both the delay controls and event controls(@... and
wait statement) are all blocking timing controls?

The first line in Page96 of SystemVerilog 3.1a LRM draft 6 read as
this:
"Statements in an always_comb shall not include those that block,
have blocking timing or event controls, or fork...join statements."
(http://www.eda.org/sv/SystemVerilog_...aft6_clean.pdf)

So I am wondering if the "blocking timing" mentioned here is just for
delay contorls.
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