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Old 07-02-2003, 04:34 AM
malexgreen
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Default question about reg and wire types

If I have an internal reg variable x[7:0] and a input port y[7:0], and
an output port port[15:0]


Is this a legal verilog assignment:

assign port = {x,y};

If it is legal verilog, are there some simulators that mess this up,
like Modelsim? Thanks.
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  #2 (permalink)  
Old 07-02-2003, 06:12 PM
Richard Iachetta
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Default Re: question about reg and wire types

In article <[email protected] >,
[email protected] says...
> If I have an internal reg variable x[7:0] and a input port y[7:0], and
> an output port port[15:0]
>
>
> Is this a legal verilog assignment:
>
> assign port = {x,y};
>
> If it is legal verilog, are there some simulators that mess this up,
> like Modelsim? Thanks.
>


Well, it looks just fine to me. I don't use Modelsim. Is Modelsim having
a problem with this for you or are you just asking?

--
Rich Iachetta
[email protected]
I do not speak for IBM.
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  #3 (permalink)  
Old 07-02-2003, 06:14 PM
John_H
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Default Re: question about reg and wire types

This should be 100% reliable. Concatenation gets a lot of use in my code; I
don't leave home without it.


"malexgreen" <[email protected]> wrote in message
news:[email protected] om...
> If I have an internal reg variable x[7:0] and a input port y[7:0], and
> an output port port[15:0]
>
>
> Is this a legal verilog assignment:
>
> assign port = {x,y};
>
> If it is legal verilog, are there some simulators that mess this up,
> like Modelsim? Thanks.



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  #4 (permalink)  
Old 07-02-2003, 06:47 PM
Ajeetha Kumari
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Default Re: question about reg and wire types

Hi,
Sounds like perfect Verilog code to me, I just tested the following
simple code on Modelsim and it works fine. Did you face any issues
with such a code?

Ajeetha,
http://www.noveldv.com

// code..
module dut (a,b);
output [15:0] a;
input [7:0] b;
assign a = { b, x};
initial
$monitor ($time," %m Value of b %b x %b a %b",b,x,a);
endmodule // dut

module tb_dut ();
wire [15:0] a;
reg [7:0] b;
reg [7:0] x;

dut d0 (a,b);
initial
begin
b <= 8'd14;
#5 b <= 8'd12;
#10 b <= 8'd22;
end
assign d0.x = x;
initial
begin
x <= 8'd14;
#5 x <= 8'd12;
#10 x <= 8'd22;
end
endmodule // tb_dut


[email protected] (malexgreen) wrote in message news:<[email protected] com>...
> If I have an internal reg variable x[7:0] and a input port y[7:0], and
> an output port port[15:0]
>
>
> Is this a legal verilog assignment:
>
> assign port = {x,y};
>
> If it is legal verilog, are there some simulators that mess this up,
> like Modelsim? Thanks.

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