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Old 04-08-2007, 10:56 AM
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I am implementing IIR Filter in verilog
with equation
a is floating point no with 5 bits
x is integer with 7 bit input .y(n) is 12 bit with 5bits
floating and 7 bit integer part
I used 2's complement logic for 1-a.
I did multiplication by shit and add.I used rounding function
for y(n) with refernce .5.My problem is i am getting limit cycle
oscillation.How to solve this as I am running out of time for
solution.Help me Thanking you

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