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  #1 (permalink)  
Old 06-06-2008, 09:02 PM
--Ross
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Default @(posedge clk) clk[=2] |->


Looking to skip first two system clocks before checking that my
next_state bus has only one bit set low

x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
next_state ) );

above didn't do it
--Ross
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  #2 (permalink)  
Old 06-07-2008, 10:52 PM
Jonathan Bromley
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Default Re: @(posedge clk) clk[=2] |->

On Fri, 6 Jun 2008 12:02:07 -0700 (PDT), --Ross
<[email protected]> wrote:

>
>Looking to skip first two system clocks before checking that my
>next_state bus has only one bit set low
>
>x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
>next_state ) );


You can never test a clock in an assertion; the sampled value
of the clock is sure to be its value as it was just before
the clock edge.

Try this instead...

assert property (@(posedge clk) 1[*2] |=> $onehot(...) );

The left-hand side will be satisfied on clock number 2, 3, 4...
and so on all the way through the sim.
--
Jonathan Bromley, Consultant

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  #3 (permalink)  
Old 06-08-2008, 07:48 PM
kookoo4systemverilog
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Default Re: @(posedge clk) clk[=2] |->

"--Ross" <[email protected]> wrote in message
news:[email protected]m...
>
> Looking to skip first two system clocks before checking that my
> next_state bus has only one bit set low
>
> x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
> next_state ) );


?!?
$onehot( !next_state )

Surely, you want the () expression to evaluate as a VECTOR and not a
single-bit?
Don't you mean $onehot( ~next_state ) ?

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