FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-25-2004, 01:17 PM
Monika Talwar
Posts: n/a
Default PLI : some stupid queries.

Hi all

May be my question sounds stupid , but i wanna know how pli works.
I actually wanna know eat are the steps that simulator follows??
And where does its behaviour differs in case of dynamic and staic linking?

I have one more question.
For Modelsim, one need to specify -pli option to vsim at the command line.
(for example: vsim -pli pli_file.so top_module)
Is there any other way of linking pli in Modelsim??

Thanks in advance
Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

All times are GMT +1. The time now is 07:40 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved