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Old 10-25-2006, 12:23 PM
crazydubi
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Default Parametrized for loop

Hi,

I am trying to do something very simple, but the simulator is having a
problem resolving my constant expressions. What would be the best
workaround for this problem. Is there something in v2000 that could be
applied that is robust for synthesis as well as for multiple
simulators?

parameter WIDTH=16;

for(i=0;i<WIDTH;i=i+1)
begin
output[i] = input1[i] | (|input2[WIDTH-1:i);
end

In vcs, I get an error that expression should be a constant.

Andreas

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Old 10-25-2006, 07:41 PM
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Default Re: Parametrized for loop


crazydubi wrote:
> Is there something in v2000 that could be
> applied that is robust for synthesis as well as for multiple
> simulators?
>
> parameter WIDTH=16;
>
> for(i=0;i<WIDTH;i=i+1)
> begin
> output[i] = input1[i] | (|input2[WIDTH-1:i);
> end


What you are trying to do requires a v2001 feature called generate.
The syntax you are using will almost work, but you will need to declare
"genvar i;" before doing it, and remove any declaration of i as
anything else. If your tools are not up to date with the latest
standard, they may also require you to put a generate-endgenerate
around the entire thing also.

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  #3 (permalink)  
Old 10-25-2006, 08:59 PM
Jurgen Schulz
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Default Re: Parametrized for loop

seems like you are trying to use less bits of input2 as i increases, hence you could try:

(input2[WIDTH-1:0]>>i)

also I assume you are not really using output as variable.

Regards, Jurgen.

crazydubi wrote:
> Hi,
>
> I am trying to do something very simple, but the simulator is having a
> problem resolving my constant expressions. What would be the best
> workaround for this problem. Is there something in v2000 that could be
> applied that is robust for synthesis as well as for multiple
> simulators?
>
> parameter WIDTH=16;
>
> for(i=0;i<WIDTH;i=i+1)
> begin
> output[i] = input1[i] | (|input2[WIDTH-1:i);
> end
>
> In vcs, I get an error that expression should be a constant.
>
> Andreas
>


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  #4 (permalink)  
Old 10-25-2006, 11:54 PM
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Default Re: Parametrized for loop


[email protected] wrote:
>
> What you are trying to do requires a v2001 feature called generate.


Oops. I should have looked at the example more closely. Since the
for-loop appeared to be at the module level, I assumed that the
assignments in the loop were continuous assignments. But clearly they
are not. This was procedural code that would appear inside an initial,
always or task.

You cannot use something like input[WIDTH-1:i] where i is a variable.
All part selects must have a constant width that can be determined at
compile time. The language requires that all expressions have a
constant width that is known at compile time, so that their evaluation
can be performed with reasonable efficiency.

As Jurgen suggested, you could use a shift to shift out the unused bits
and reduce that. The zeroes shifted in will not affect the reduction
result. Or you could generate a mask to AND off the unused bits before
the reduction. Or you could use a nested loop to do the reduction of
the desired bits. This would be pretty inefficient, since each time
you would be computing almost the same thing as last time, with one
less bit included. It would be more efficient to use one loop that
computes the shortest reduction first, and then combines one more bit
into the previously computed result each time around.

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