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Old 03-26-2007, 10:19 PM
Verictor
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Default parameter range specification

Hi,

When specifying the following parameter

parameter [3:0] RESET = 4'b0000;

the synthesis tool reports this warning:

Parameter range specification is new feature of Verilog 2001.
Synthesis and non-Verilog 2001 compatible simulation may have
different results. (VER-311)

How do I ensure the synthesis and simulation will have the same
results? Or what is this warning for?

Thanks

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Old 03-27-2007, 03:28 AM
Ajeetha (www.noveldv.com)
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Default Re: parameter range specification

Hi,

On Mar 27, 1:19 am, "Verictor" <[email protected]> wrote:
> Hi,
>
> When specifying the following parameter
>
> parameter [3:0] RESET = 4'b0000;
>
> the synthesis tool reports this warning:
>
> Parameter range specification is new feature of Verilog 2001.
> Synthesis and non-Verilog 2001 compatible simulation may have
> different results. (VER-311)


I would say you can safely ignore this warning (or turn it off once
you check your sim support). This just says that if you use a HDL
simulator that doesn't support this style, you *may* have mismatches.
But as far as I've seen, simulators are usually ahead in language
support than synthesis tools. Even free tools like Icarus is V2K
compliant to a large extent (I didn;t check this specific stuff
though).

So make sure you run your simulation before synthesis, if that went
through fine, ignore this warning.

Regards
Ajeetha, CVC
www.noveldv.com

>
> How do I ensure the synthesis and simulation will have the same
> results? Or what is this warning for?
>
> Thanks



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