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Old 05-07-2005, 08:53 PM
Tomek Zieliński
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Default [Newbie] Output pins are stuck at VCC or GND

Helo!

This is ma first code in Verilog. It is simple clock.

module zegar(clk);
output clk;
reg clk;
parameter period=500;
always begin
#(period/2) clk=1;
#(period/2) clk=0;
end
endmodule

There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
stuck at GND.
What is wrong?

Best Regards
Thomas Zielinski


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  #2 (permalink)  
Old 05-07-2005, 10:54 PM
info_
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Default Re: [Newbie] Output pins are stuck at VCC or GND

Tomek Zieliński wrote:
> Helo!
>
> This is ma first code in Verilog. It is simple clock.
>
> module zegar(clk);
> output clk;
> reg clk;
> parameter period=500;
> always begin
> #(period/2) clk=1;
> #(period/2) clk=0;
> end
> endmodule
>
> There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
> stuck at GND.
> What is wrong?
>
> Best Regards
> Thomas Zielinski
>
>



Are you describing actual silicon ?

This code is for simulation : it is a stimulus.

You are trying to synthesize this behaviour into gates (LUts)
and Flip Flops : no way.

An FPGA usually has a clock _input_.

I suggest you read some literature about FPGAs, synthesis, HDLs
etc... before running the tools, otherwise you will run into
a lot of trouble and have none of the great fun FPGA Design
may provide.
My opinion indeed.

Bert Cuzeau
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  #3 (permalink)  
Old 05-09-2005, 02:33 PM
Mike Lewis
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Posts: n/a
Default Re: [Newbie] Output pins are stuck at VCC or GND


"Tomek Zieliński" <[email protected]> wrote in message
news:[email protected]
> Helo!
>
> This is ma first code in Verilog. It is simple clock.
>
> module zegar(clk);
> output clk;
> reg clk;
> parameter period=500;
> always begin
> #(period/2) clk=1;
> #(period/2) clk=0;
> end
> endmodule
>
> There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
> stuck at GND.
> What is wrong?
>
> Best Regards
> Thomas Zielinski
>
>


try removing the clk=0 and changing the clk=1 to clk=!clk.

And as the other poster mentioned this is only particular to
the simulation environemnt and cannot be synthesized.


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