FPGA Central

I would like to make a full adder from two half adder. I use a
hierarchial
model for the the full adder.

How do I connect a output of one instance with a input of anther I
tried declaring a wirer to connect the two I received a" warning port
miss match".

//code:
//combination 2 half adder, not working

module FullAdder (sum, carry, a,b, carry_out);
input carry;
input a, b;
output carry, sum;
output carry_out;

HalfAdd low( a[a], b[sum1], sum[sum], carry_out[carry]);

HalfAdd hi ( a[1], b[1], sum[1], carry[1]);

or(carry_out, carry[0], carry[1]);

endmodule

So that we can help you, do you know much about
1) Module instantiation syntax, and
2) multi-bit wires and indicies
?
Your code as you have presented it makes little to no sense.
Also, just curious - does your professor want you to use the "or" primitive
instantiation rather than using a simple "assign?"


"slxrti" <[email protected]> wrote in message
news:[email protected] om...
> I would like to make a full adder from two half adder. I use a
> hierarchial
> model for the the full adder.
>
> How do I connect a output of one instance with a input of anther I
> tried declaring a wirer to connect the two I received a" warning port
> miss match".
>
> //code:
> //combination 2 half adder, not working
>
> module FullAdder (sum, carry, a,b, carry_out);
> input carry;
> input a, b;
> output carry, sum;
> output carry_out;
>
> HalfAdd low( a[a], b[sum1], sum[sum], carry_out[carry]);
>
> HalfAdd hi ( a[1], b[1], sum[1], carry[1]);
>
> or(carry_out, carry[0], carry[1]);
>
> endmodule