FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-16-2005, 02:17 PM
Prime
Guest
 
Posts: n/a
Default Newb: Help with decoder/latch

Hi, I am trying to replace an LS573 latch with a CPLD (because in future
I want to be able to do address decoding as well as latching, and a CPLD
will keep my chip count down). But am running into problems, here is my
current code :-

odule avrinterface(AD,RD,WR,ALE,Ahigh,Addr,Dram,CS,RRD,R WR);
input RD; // RD from AVR
input WR; // WR from AVR
input ALE; // Address Latch from AVR
input Ahigh; // High address lines [8..15] from AVR

output [15:0] Addr; // Address lines to RAM
output CS; // Chip select to RAM
output RRD; // RD to ram
output RWR; // WR to ram

inout AD; // Multiplexed low address lines/data lines
from AVR
inout Dram; // Data lines to/from RAM

reg [7:0] Alow = 8'h00;
reg [7:0] DataBuf = 8'h00;
reg [15:0] Addr = 16'h0000;

wire [7:0] Dramin;

assign RRD = RD;
assign RWR = WR;
assign CS = 0;

assign Dramin = Dram;

assign AD = RD ? DataBuf : 8'bz;
assign Dram = WR ? DataBuf : 8'bz;

always @(posedge ALE or posedge RD or posedge WR)
begin
if (ALE == 1)
begin
Alow <= AD;
Addr <= {Ahigh,Alow};
end

if (RD == 1)
begin
DataBuf <= Dramin;
end

if (WR == 1)
begin
DataBuf <= AD;
end
end

endmodule


The latch is used to interface an AVR microcontroler to some standard
SRAM, the AVR multiplexes the bottom 8 address bits and the data bits on
the same port, the top address bits are not multiplexed. The ALE signal
determines if the multiplexed port is data or address, High=Address, RD
and WR are standard active high Read and Write signals.

The problem I get is that when I try and synthisise the above code I get
:-

ERROR:Xst:899 - avrinterface.v line 38: The logic for <Alow> does not
match a known FF or Latch template.
ERROR:Xst:899 - avrinterface.v line 39: The logic for <Addr> does not
match a known FF or Latch template.

If I comment out the if (WR == 1) and the posedge WR in the always, it
compiles but I get a bucket load of errors from "translate" :-

WARNING:Xst:646 - Signal <DataBuf<7:1>> is assigned but never used.
WARNING:Xst:737 - Found 16-bit latch for signal <Addr>.
WARNING:Xst:737 - Found 8-bit latch for signal <Alow>.
WARNING:Xst:737 - Found 8-bit latch for signal <DataBuf>.
WARNING:Xst:1710 - FF/Latch <Addr_12> (without init value) is constant
in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_11>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_10>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_9>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_14>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_15>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_4>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_3>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_2>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_1>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_6>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_7>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_13>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Alow_5>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_1>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_2>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_3>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_4>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_5>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_6>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Addr_7>
(without init value) is constant in block <avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_5> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_7> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_6> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_1> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_2> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_3> is unconnected in block
<avrinterface>.
WARNING:Xst:1291 - FF/Latch <DataBuf_4> is unconnected in block
<avrinterface>.



Does anyone know what I am doing wrong or have any sugestions of how to
fix it.

Cheers.

Phill.
Reply With Quote
  #2 (permalink)  
Old 01-17-2005, 01:50 PM
Guest
 
Posts: n/a
Default Re: Newb: Help with decoder/latch

Hi,
your descrition inside the edge clocked process dosent match any
realizable logic element, thats the reason its complaining. when you
use edges of clock then you cannot have parallel if constructions, you
have to use if-else-else if constructs. Or you will have to remove the
posedge constructs from your sentivity list- which will give latches.

Reply With Quote
  #3 (permalink)  
Old 01-18-2005, 08:06 AM
Paul Uiterlinden
Guest
 
Posts: n/a
Default Re: Newb: Help with decoder/latch

Prime wrote:
> Hi, I am trying to replace an LS573 latch with a CPLD (because in future
> I want to be able to do address decoding as well as latching, and a CPLD
> will keep my chip count down). But am running into problems, here is my
> current code :-
>
> odule avrinterface(AD,RD,WR,ALE,Ahigh,Addr,Dram,CS,RRD,R WR);
> input RD; // RD from AVR
> input WR; // WR from AVR
> input ALE; // Address Latch from AVR
> input Ahigh; // High address lines [8..15] from AVR
>
> output [15:0] Addr; // Address lines to RAM
> output CS; // Chip select to RAM
> output RRD; // RD to ram
> output RWR; // WR to ram
>
> inout AD; // Multiplexed low address lines/data lines
> from AVR
> inout Dram; // Data lines to/from RAM
>
> reg [7:0] Alow = 8'h00;
> reg [7:0] DataBuf = 8'h00;
> reg [15:0] Addr = 16'h0000;
>
> wire [7:0] Dramin;
>
> assign RRD = RD;
> assign RWR = WR;
> assign CS = 0;
>
> assign Dramin = Dram;
>
> assign AD = RD ? DataBuf : 8'bz;
> assign Dram = WR ? DataBuf : 8'bz;
>
> always @(posedge ALE or posedge RD or posedge WR)
> begin
> if (ALE == 1)
> begin
> Alow <= AD;
> Addr <= {Ahigh,Alow};
> end
>
> if (RD == 1)
> begin
> DataBuf <= Dramin;
> end
>
> if (WR == 1)
> begin
> DataBuf <= AD;
> end
> end
>
> endmodule
>
>
> The latch is used to interface an AVR microcontroler to some standard
> SRAM, the AVR multiplexes the bottom 8 address bits and the data bits on
> the same port, the top address bits are not multiplexed. The ALE signal
> determines if the multiplexed port is data or address, High=Address, RD
> and WR are standard active high Read and Write signals.
>
> The problem I get is that when I try and synthisise the above code I get
> :-
>
> ERROR:Xst:899 - avrinterface.v line 38: The logic for <Alow> does not
> match a known FF or Latch template.
> ERROR:Xst:899 - avrinterface.v line 39: The logic for <Addr> does not
> match a known FF or Latch template.


The template you are using for a latch is not correct. It should be:

always @(en, din)
if (en)
qout <= din;

Furthermore, you cannot combine different enables into one always block.
So the correct way is:

always @(ALE or AD or Ahigh or Alow)
if (ALE)
begin
Alow <= AD;
Addr <= {Ahigh,Alow};
end


Hmm, for DataBuf you need something more: a mux followed by a latch, I
suppose.

assign DB = RD ? Dramin : AD;
always @(RD or WR or Dramin)
if (RD | WR)
DataBuf <= DB;

All untested of course.

Paul.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Newb Reccomend a Verilog book. Prime Verilog 1 01-03-2005 05:37 PM
FF/Latch Trimming : Xilinx ISE 6.3i erjs Verilog 1 12-02-2004 07:36 PM
Re: Rotating priority interupt decoder/selector Brian Guralnick Verilog 3 06-30-2004 01:07 AM
latch and shift 15 bits. Denis Gleeson Verilog 5 11-08-2003 06:59 PM


All times are GMT +1. The time now is 11:59 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved