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Old 10-20-2005, 03:54 PM
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Default Ncverilog PLI problem

I have written small code in C which I want to use as PLI. I have
compiled it for ncverilog in linux. I have pasted code below. But I am
getting stack overflow error. I have pasted that below. Please help me
out. I have compiled code like this

gcc -I($PLIINC) -c dprintf.c -o dummy.o
gcc -shared -shared-libgcc -o dummy.so dummy.o -lpthread

include <stdarg.h>

#include <stdlib.h>
#include "vxl_veriuser.h"
//#include "acc_user.h"

extern void dprintf(void)
printf("Dummy print\n");

p_tfcell my_bootstrap()
static s_tfcell my_tfs[2] = {
{usertask, 0, 0, 0, dprintf, 0,
"$my_dummyprintf", 1},

printf(" Registering $my_dummy_printf task\n");

ncsim: *internal* (sv_seghandler - trapno -1).
Observed simulation time : 11961812 PS + 0
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
***Current stack trace:
-->[User Code ] 0x400ad7aa <don't know>
-->[User Code ] 0x400934c7 _IO_vfprintf + 137
-->[User Code ] 0x400b6c0b vdprintf + bb
-->[User Code ] 0x4009c15d dprintf + 2d
-->[TF CB Support ] 0x8123e2f <don't know>
-->[VPI Overhead ] 0x815e10a <don't know>
***Verilog source where error occurs:
$my_dummyprintf(...) (PLI calltf)
Module: exercise
Instance: test_top.exercise
File: ./test.vh
Line: 127
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.

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