FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-06-2006, 05:02 AM
Prashanth
Guest
 
Posts: n/a
Default ncverilog: command line options

Hi All,

I am new to NCverilog.
I am using it to compile my design, in the command line.

The contents of the command line arguments file look similar to this

// header files
-v ..\includes\xxx.h
-v ..\includes\yyy.h
// source files
..\src\abc.v
..\src\xyz.v

I am using the -f command line option to pass the above information.
I get an error during compilation saying "cannot open the include file
xxx.h" or "cannot open the include file yyy.h"
and it seems to be seraching for the include file under "src" directory not
under "includes".

is there a different command line option that I need to be using for the
header files ?

Thanks
Prashanth


Reply With Quote
  #2 (permalink)  
Old 03-06-2006, 09:55 AM
Guest
 
Posts: n/a
Default Re: ncverilog: command line options

1. If you are using linux/unix you should use forward slashes
2. use just " -v ../includes"

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
defining a string macro from ncverilog command line Jason Zheng Verilog 2 03-30-2005 01:28 AM
VirSim command line chainastole Verilog 2 02-14-2005 06:57 PM
dw_prefer_mc_inside command in DC whizkid Verilog 1 10-29-2004 12:43 PM
Verilog Options Bill82 Verilog 0 10-20-2004 11:54 AM
Equivalent indent command for Verilog Javier Castillo Verilog 0 08-30-2004 06:07 PM


All times are GMT +1. The time now is 07:35 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved