FPGA Central

I am trying to use named event to emulate the request and
acknowledgement.
I think I can detect the event by hierarchical naming convention in
module connection trees.
However, I think by doing so, the testbench code is not quite scalable
since I cannot see the event from the module top.

I would like to ask can I have named event port in module definition?

Thanks

Robert Au wrote:
>
> I would like to ask can I have named event port in module definition?

Not in Verilog. I believe it can be done in SystemVerilog.

[email protected] 寫道：

> Robert Au wrote:
> >
> > I would like to ask can I have named event port in module definition?
>
> Not in Verilog. I believe it can be done in SystemVerilog.

I read through the SV spec, but couldn't find something similar.
However, I would say, in SV we can use mailbox or semaphore to perform
similar task.

Robert Au wrote:
> [email protected] 寫道：
>
> > Not in Verilog. I believe it can be done in SystemVerilog.
>
> I read through the SV spec, but couldn't find something similar.
> However, I would say, in SV we can use mailbox or semaphore to perform
> similar task.

It may not say it explicitly, but it does say that variables of all
types can be passed through ports. Also, the operation of an assignment
of one named event to another is defined, as is the behavior of a
continuous assignment of a variable to a variable. That provides a
definition of what it means to pass a named event through a port.

As Steve said, in SystemVerilog you can pass events as module ports.
But hold on - do you want simple events or some "status/data"
associated with that event (not always perhaps, but some times?) - this
is where VMM Notification (See: www.vmm-sv.org) fits the bill perfectly
for TBs. If you use VCS, I suggest you look at it right away, even
otherwise I'm sure other vendors promote methodologies quite similar,
so talk to them.

HTH
Ajeetha, CVC
www.noveldv.com

Robert Au wrote:
> I am trying to use named event to emulate the request and
> acknowledgement.
> I think I can detect the event by hierarchical naming convention in
> module connection trees.
> However, I think by doing so, the testbench code is not quite scalable
> since I cannot see the event from the module top.
>
> I would like to ask can I have named event port in module definition?
>
> Thanks