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  #1 (permalink)  
Old 08-10-2004, 11:03 AM
Rolf Kemper
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Default multiplexer from slice / paremeter on with

Hi All,

I have a small challange on code below. The mux_select is actully a
the output from a counter. Width is fixed here but may be also
parameterized as the result_save rergister.
My target is to read out the register in slices of 8 bit by a counter.
As register length is variable by a parameter the counter length is
vaiable too.

Verilog does not allow to have variables in a range as far I undestood
it.
So assign mux_out = result_save[ ( multiplier_width - 1) - 8 *
mux_select : ..... will not work.

assign mux_out =
( mux_select == 3'b000 ) ? result_save[multiplier_width -
1 : multiplier_width - 8] : // msb first 63 :56
( mux_select == 3'b001 ) ? result_save[multiplier_width -
9 : multiplier_width - 16] :
( mux_select == 3'b010 ) ? result_save[multiplier_width -
17 : multiplier_width - 24] :
( mux_select == 3'b011 ) ? result_save[multiplier_width -
25 : multiplier_width - 32] :
( mux_select == 3'b100 ) ? result_save[multiplier_width -
33 : multiplier_width - 40] :
( mux_select == 3'b101 ) ? result_save[multiplier_width -
41 : multiplier_width - 48] :
( mux_select == 3'b110 ) ? result_save[multiplier_width -
49 : multiplier_width - 56] :
( mux_select == 3'b111 ) ? result_save[multiplier_width -
57 : multiplier_width - 64] :
0;

The code above is so-far OK, but has clearly the disadvantage that it
is not really parameterized. In case the register is bigger than 64
bit I need to add statements.

What is the best way to code and RTL which is really parameterized ???

A second thing would be to parameterise this

parameter MyWidth = 5;
5'b0 can not be written as MyWidth'b0

Any idea to solve this ?

Thanks a lot for your hints

Rolf
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  #2 (permalink)  
Old 08-10-2004, 11:23 AM
Jonathan Bromley
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Default Re: multiplexer from slice / paremeter on with

On 10 Aug 2004 02:03:04 -0700, [email protected]
(Rolf Kemper) wrote:

>Hi All,
>
>I have a small challange on code below.


Let's do the easy one first:

>A second thing would be to parameterise this
>
> parameter MyWidth = 5;
> 5'b0 can not be written as MyWidth'b0


But you can use a replication:
{ MyWidth {1'b0} }

>My target is to read out the register in slices of 8 bit by a counter.
>As register length is variable by a parameter the counter length is
>vaiable too.
>Verilog does not allow to have variables in a range as far I undestood
>it.


Correct.

>So assign mux_out = result_save[ ( multiplier_width - 1) - 8 *
>mux_select : ..... will not work.


Two possibilities:

(a) use a "for" loop to copy the bits one by one. Of course,
in hardware you copy all the bits simultaneously - it's
just a way of rewriting the copy so that each bit is
specified separately.

reg [7:0] mux_result; // must be a reg
always @(result_save or mux_select) begin : selector
integer i;
for (i=0; i < 8; i = i + 1)
mux_result[i] = result_save[mux_select*8 + i];
end
assign mux_out = mux_result;

(b) use Verilog-2001 indexed part select, if your tools
support Verilog-2001:

assign mux_out = result_save[mux_select*8 +: 8];

The +: construct indicates that "mux_select*8" is the
lowest-numbered index to be chosen (it can be variable)
and "8" is the width of the slice (must be constant).

All of this can readily be parameterised for width
of the slice, number of slices in the word, etc.
--
Jonathan Bromley, Consultant

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  #3 (permalink)  
Old 08-10-2004, 05:52 PM
John_H
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Default Re: multiplexer from slice / paremeter on with

For your multiplexed assignment, if mux_out is already 8 bits try:

assign mux_out = result_save >> (multiplier_width - 8 * (mux_select+1) );


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