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Old 07-21-2003, 05:48 PM
Eric Peterson
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Default multiple task 'instances'


I'm trying to use Verilog tasks to make my code more structured, but
am running into a potential limitation - there seems to be no concept
of multiple 'instances' of a task. If this seems confusing, what I'm
running up against is the way Verilog has only a single copy of all
task-scoped variables - each caller shares those same variables. I'm
looking to have separate ('per-instance') copies of those variables.

So my question is, is there a way to have multiple instances of a
task, each with their own independent task variables? Can one have a
vector of tasks? If not, then is there a conventional way to do this,
say keeping external task 'state' in an array (per instance) and pass
that state as an inout variable?

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