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  #1 (permalink)  
Old 09-02-2005, 10:51 AM
vssumesh
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Default Multidimensional port.

Hello all
Is it possible to instantiate multi dimensional input/output port in
verilog2001.
I tried the following code.

module A(in,out);
input [7:0]in[7:0];
output [7:0]out[7:0];

but it did gave an error in the Xilinx ISE 6.2....

Sumesh

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Old 09-02-2005, 06:13 PM
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Default Re: Multidimensional port.


vssumesh wrote:
> Is it possible to instantiate multi dimensional input/output port in
> verilog2001.


No.

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  #3 (permalink)  
Old 09-03-2005, 11:12 AM
Svilen
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Default Re: Multidimensional port.

If I remember correctly according to the System Verilog standard it
should be possible. I haven't seen it implemented yet. At least the
latest ncverilog is complaining about multidimentional ports (packed)
and multidimentional parameters.

Svilen

vssumesh wrote:
> Hello all
> Is it possible to instantiate multi dimensional input/output port in
> verilog2001.
> I tried the following code.
>
> module A(in,out);
> input [7:0]in[7:0];
> output [7:0]out[7:0];
>
> but it did gave an error in the Xilinx ISE 6.2....
>
> Sumesh
>

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  #4 (permalink)  
Old 09-03-2005, 07:33 PM
raul
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Default Re: Multidimensional port.

Hi,

Why don't you use 63:0 input/output ports and then read/write
individual bytes inside your module?

RAUL

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