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Old 05-24-2004, 07:50 AM
shragafr
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Default module inside module problem.

Hello.

I wrote code in verilog that recieve serial data,convert it to parrallel
word and convert it from binary to bcd, and from bcd to 7 segment.

the "binary to bcd" and "bcd to 7 segment" are separete
modules (different .v files).
I tried to use them from ALWAYS block but the top module does'nt recognize
these modules.
when I get tese files out of the always loop the top module start
to "see" these files.

In addition the output of this module can't be connected to registers.

Does anybody know the reasone for this???

thank in advance
shraga.
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Old 05-24-2004, 11:06 AM
Student
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Default Re: module inside module problem.

dun understand your question...

Kelvin




"shragafr" <[email protected]> wrote in message
news:[email protected] om...
> Hello.
>
> I wrote code in verilog that recieve serial data,convert it to parrallel
> word and convert it from binary to bcd, and from bcd to 7 segment.
>
> the "binary to bcd" and "bcd to 7 segment" are separete
> modules (different .v files).
> I tried to use them from ALWAYS block but the top module does'nt recognize
> these modules.
> when I get tese files out of the always loop the top module start
> to "see" these files.
>
> In addition the output of this module can't be connected to registers.
>
> Does anybody know the reasone for this???
>
> thank in advance
> shraga.



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  #3 (permalink)  
Old 05-24-2004, 08:03 PM
Andy Peters
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Default Re: module inside module problem.

[email protected] (shragafr) wrote in message news:<[email protected] com>...
> I wrote code in verilog that recieve serial data,convert it to parrallel
> word and convert it from binary to bcd, and from bcd to 7 segment.
>
> the "binary to bcd" and "bcd to 7 segment" are separete
> modules (different .v files).
> I tried to use them from ALWAYS block but the top module does'nt recognize
> these modules.
> when I get tese files out of the always loop the top module start
> to "see" these files.


Are you telling us that you put the module instantiations INSIDE an
always block? If so, then you need to run, not walk, to your nearest
bookseller and purchase a Verilog text.

> In addition the output of this module can't be connected to registers.
>
> Does anybody know the reasone for this???


Your new Verilog book will explain this, but in a nutshell, an output
port can not be connected externally to a type reg.

--a
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