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  #1 (permalink)  
Old 05-09-2006, 02:59 PM
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Default Modeling a serial port in Verilog.

Hi All,
I need to develop a serial port model (with most of the functionalities
such as adjustable data width, parity, number of stop bits etc) in
Verilog. Could anyone of you guide me towards any good links for the
same ?

Thanks in advance,
Amit.

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  #2 (permalink)  
Old 05-09-2006, 03:18 PM
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Default Re: Modeling a serial port in Verilog.

>I need to develop a serial port model (with most of the functionalities
>such as adjustable data width, parity, number of stop bits etc) in
>Verilog. Could anyone of you guide me towards any good links for the
>same ?
>
>Thanks in advance,


There's a lot of information here: http://google.com/
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  #3 (permalink)  
Old 05-09-2006, 03:22 PM
gabor
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Default Re: Modeling a serial port in Verilog.


[email protected] wrote:
> >I need to develop a serial port model (with most of the functionalities
> >such as adjustable data width, parity, number of stop bits etc) in
> >Verilog. Could anyone of you guide me towards any good links for the
> >same ?
> >
> >Thanks in advance,

>
> There's a lot of information here: http://google.com/


or better:

http://www.opencores.org/browse.cgi/by_category

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  #4 (permalink)  
Old 05-10-2006, 05:24 AM
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Default Re: Modeling a serial port in Verilog.

Couldn't get any relevant links in the top 20 results.

-A.

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  #5 (permalink)  
Old 05-10-2006, 05:24 AM
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Default Re: Modeling a serial port in Verilog.

Thanks a lot Gabor.

-Amit.

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  #6 (permalink)  
Old 05-10-2006, 09:46 AM
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Default Re: Modeling a serial port in Verilog.

>Couldn't get any relevant links in the top 20 results.
>
>-A.


Just post your query again in this group. After all, that's what
we're here for - to look through all those Google pages for you when
you get tired after the first two.
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  #7 (permalink)  
Old 05-10-2006, 10:20 AM
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Default Re: Modeling a serial port in Verilog.

> Just post your query again in this group. After all, that's what
> we're here for - to look through all those Google pages for you when
> you get tired after the first two.


Sincere apologies Mike,
Henceforth, I shall be really, *really* careful and will first do my
homework before posting a query.

Sorry again.

Have a nice day.
Amit.

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  #8 (permalink)  
Old 05-11-2006, 02:27 AM
Rob
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Default Re: Modeling a serial port in Verilog.

You could also go to opencores.org and see a real example.


<[email protected]> wrote in message
news:[email protected] ups.com...
> Hi All,
> I need to develop a serial port model (with most of the functionalities
> such as adjustable data width, parity, number of stop bits etc) in
> Verilog. Could anyone of you guide me towards any good links for the
> same ?
>
> Thanks in advance,
> Amit.
>



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  #9 (permalink)  
Old 05-11-2006, 07:28 AM
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Default Re: Modeling a serial port in Verilog.

Rob wrote:
> You could also go to opencores.org and see a real example.


Hi Rob,
Thanks a lot. I already checked out opencores.org and the material in
there is indeed good.

Regards,
Amit.

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  #10 (permalink)  
Old 05-15-2006, 12:30 AM
Andy Peters
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Default Re: Modeling a serial port in Verilog.

[email protected] wrote:
> Couldn't get any relevant links in the top 20 results.


How about searching for "Verilog UART" ?

-a

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  #11 (permalink)  
Old 05-15-2006, 05:39 AM
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Default Re: Modeling a serial port in Verilog.

Andy Peters wrote:
> How about searching for "Verilog UART" ?


Hi Andy,
Many thanks for your help.

Regards,
Amit.

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