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Old 03-08-2007, 07:02 PM
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Default Missing information in SimVision


New here :-).

I'm an analog designer trying to create a Verilog representation of a
very large circuit I'm putting together so that other members of the
group can tie my circuits into their models. I've written gate level
code for everything and I then let NC Verilog do the rest as far as
putting together a netlist and then simulating.

A couple of months ago, I had written some code for an ideal DAC and
simulated it. I would open up SimVision, and I could look at the
values for each node for each time step. Now, when I try the same
thing, the only data available in SimVision is the last time point in
the simulation. What do I need to change to make the data visible for
all time points?


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