FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-10-2003, 11:06 PM
Scott Brady Drummonds
Guest
 
Posts: n/a
Default Making a System Call After Simulation

Hi, everyone,

I'm a Verilog novice and am trying to have my compiled circuit execute a PLI
routine after simulation is complete (to write out some data I've collected
during simulation). However, I have no idea how to do this. My stimulus is
provided in EVCD format, so it appears that just adding my call to that file
doesn't work.

How can I register my function to be called as simulation completes?

Thanks!
Scott

--
Remove ".nospam" from the user ID in my e-mail to reply via e-mail.


Reply With Quote
  #2 (permalink)  
Old 10-13-2003, 06:19 AM
Steve Meyer
Guest
 
Posts: n/a
Default Re: Making a System Call After Simulation

It is easy. Just register a cbEndOfSimulation call back. If
your simulator supports modern +load_vpi= option, easiest is to register
the call back in one of the [booststrap routine list] routines.
You can see an example that uses this callback in the vacbtst.c
program in the tests_and_examples directory of our gpl-cver
release (home: www.pragmatic-c.com/gpl-cver).
/Steve


On Fri, 10 Oct 2003 15:06:10 -0700, Scott Brady Drummonds
<[email protected]> wrote:
> Hi, everyone,
>
> I'm a Verilog novice and am trying to have my compiled circuit execute a PLI
> routine after simulation is complete (to write out some data I've collected
> during simulation). However, I have no idea how to do this. My stimulus is
> provided in EVCD format, so it appears that just adding my call to that file
> doesn't work.
>
> How can I register my function to be called as simulation completes?
>
> Thanks!
> Scott
>



--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: [email protected]
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402
Reply With Quote
  #3 (permalink)  
Old 10-13-2003, 06:22 PM
Scott Brady Drummonds
Guest
 
Posts: n/a
Default Re: Making a System Call After Simulation


"Steve Meyer" <[email protected]> wrote in message
news:[email protected] ..
> It is easy. Just register a cbEndOfSimulation call back.


Steve,

After following your suggestion to some more resources, I found out that my
simulator--VCS--doesn't support cbEndOfSimulation. It does, however,
provide another mechanism (vcs_atexit(void (*)(int)) that provides a similar
function.

Thank you so much for the pointer. It got me on the right track!

Scott


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 02:05 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved