FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 12-13-2004, 05:29 PM
Vick
Guest
 
Posts: n/a
Default Making output-port to bi-directional-port!

Hello everyone,

I am facing problems making an output-port to a bi-directional port.

//////////////////////////////////////////////////////
///// (A) Here is the code, which compiles correctly:
/////////////////////////////////////////////////////
module SRAMinterface (AD,clock, WE, RE)

input clock;
input WE;
input RE;


output [31:0] AD;
reg [31:0] AD;

reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;

reg E,F;

always @(posedge clock)
begin
if (E==F)
begin
assign AD = {A,B,C,D};
end

else assign AD = 8'hzzzzzzzz;
end
end
endmodule


/////////////////////////////////////////////////////////////////
//// (B) Here is the Code, which gives the error as shown below:
////////////////////////////////////////////////////////////////

module SRAMinterface (AD,clock, WE, RE)

input clock;
input WE;
input RE;


inout [31:0] AD; // Note: This gives error when AD declared as
inout-port //
reg [31:0] AD; // Declaring: wire [31:0] AD also didnt compile!

reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;

reg E,F;

always @(posedge clock)
begin
if (E==F)
begin
assign AD = {A,B,C,D};
//// The error is shown at this line saying Incompatible inout port
////
end

else assign AD = 8'hzzzzzzzz;
end
end
endmodule



I tried the following but none of them compiled:

(1) I know that Inout-ports both internally & externally must always
be net type. So I declared: <wire [31:0] AD > in (B) above

(2) The LRM clearly says that any continuous assignment within any
procedural-statements, namely always (or) initial, has to be a
register, So retained AD as reg while it was declared inout-port.


(3) I also rememeber reading earlier that the Conditional-assignment
needs to be used for bi-directional ports.

So I replaced the above always @(..) block to a conditional assignment
as below:

assign AD = (E==F) ? {A,B,C,D} : 8'hzzzzzzzz;


Is there soemthing very obvious, I am missing!!
Reply With Quote
  #2 (permalink)  
Old 12-14-2004, 06:59 AM
Paul Uiterlinden
Guest
 
Posts: n/a
Default Re: Making output-port to bi-directional-port!

Vick wrote:
> Hello everyone,
>
> I am facing problems making an output-port to a bi-directional port.
> [snip]
>
> inout [31:0] AD; // Note: This gives error when AD declared as
> inout-port //
> reg [31:0] AD; // Declaring: wire [31:0] AD also didnt compile!


One does not preclude the other. AD can be inout and reg at the same time:

inout [31:0] AD;
reg [31:0] AD;

Since Verilog 2001 the two lines can be combined into one line (if I'm
not mistaken):

inout reg [31:0] AD;

> [snip]
>
> else assign AD = 8'hzzzzzzzz;


This should be 32'hzzzzzzzz;. It don't know what happens in your case,
specifying the width as 8, supplying 32 bits. I don't know Verilog that
well.

Paul.
Reply With Quote
  #3 (permalink)  
Old 12-14-2004, 10:46 AM
Bernd Beuster
Guest
 
Posts: n/a
Default Re: Making output-port to bi-directional-port!

Vick wrote:

> always @(posedge clock)
> begin
> if (E==F)
> begin
> assign AD = {A,B,C,D};
> //// The error is shown at this line saying Incompatible inout port
> ////
> end
>
> else assign AD = 8'hzzzzzzzz;
> end
> end


Leave out `assign'. Also write 32'bz instead of 8'bz....z.
For clocked processes use the non-blocking operator `<='.

Reply With Quote
  #4 (permalink)  
Old 12-15-2004, 12:09 AM
Guest
 
Posts: n/a
Default Re: Making output-port to bi-directional-port!


Vick wrote:
>
> I am facing problems making an output-port to a bi-directional port.
>
> //////////////////////////////////////////////////////
> ///// (A) Here is the code, which compiles correctly:
> //////////////////////////////////////////////////////
> assign AD = {A,B,C,D};


Independent of what you are trying to do, you don't want to have
the keyword "assign" here. That makes this a "procedural continuous
assignment" or "quasi-continuous assignment", which is much like a
"force" statement. What you want here is a simple blocking assignment
to the reg: " AD = {A,B,C,D};" Don't use "assign" inside procedural
code (unless you understand what it means and know that is what you
really want).

> I tried the following but none of them compiled:
>
> (1) I know that Inout-ports both internally & externally must always
> be net type. So I declared: <wire [31:0] AD > in (B) above


But it is illegal to assign to a wire from procedural code, as you
note in 2 below.

> (2) The LRM clearly says that any continuous assignment within any
> procedural-statements, namely always (or) initial, has to be a
> register, So retained AD as reg while it was declared inout-port.


But it is illegal to have an inout port declared as reg, as you note
in 1 above.

You must satisfy both restrictions.

A wire must be driven by drivers (gates, continuous assignments), and
cannot be assigned in procedural code as if it were a variable. A reg
acts like a variable, but cannot be driven by drivers (which means no
multiple driver resolution), and cannot pass through a port, and cannot
be connected to an inout port. An output reg port is just short-hand
for a variable inside the module with an implicit continuous assignment
through the port to a net on the outside.

To make this work, you need an inout port which is a net, both inside
and outside the module. But then you can't use the short-hand for the
implicit continuous assignment from a reg to the net. If you want to
drive a value onto the net from the local source, you will need to do
so with an explicit continuous assignment.

> (3) I also rememeber reading earlier that the Conditional-assignment
> needs to be used for bi-directional ports.
>
> So I replaced the above always @(..) block to a conditional

assignment
> as below:
>
> assign AD = (E==F) ? {A,B,C,D} : 8'hzzzzzzzz;


If you replaced the entire always block (which assigned to a reg) with
a continuous assignment that drives the wire AD, this should work.
That
would satisfy the requirements that the inout port be a net, and that
the net was driven by drivers, not procedural assignments.

Alternately, you could keep the always block and have it assign to an
intermediate reg, then have an explicit continuous assignment of the
reg value to the net.

Reply With Quote
  #5 (permalink)  
Old 12-15-2004, 12:30 AM
Guest
 
Posts: n/a
Default Re: Making output-port to bi-directional-port!


Paul Uiterlinden wrote:
>
> One does not preclude the other. AD can be inout and reg at the same

time:

No, it can't. Only an output port can also be declared as a reg. In
that case, it is essentially a short-hand for a local reg with an
implicit
continuous assignment from the reg to the net on the outside of the
port.

The "sink" or "destination" side of a port connection must always be a
net (the outside of an output port, or the inside of an input port).
The
"source" side of a port connection (the outside of an input port, or
the
inside of an output port) can be a reg. In this case there is
essentially
a continuous assignment from the source side to the sink side.
For an inout port, both sides must be nets.

Reply With Quote
  #6 (permalink)  
Old 12-15-2004, 06:03 AM
Paul Uiterlinden
Guest
 
Posts: n/a
Default Re: Making output-port to bi-directional-port!

[email protected] wrote:
> Paul Uiterlinden wrote:
>
>>One does not preclude the other. AD can be inout and reg at the same

>
> time:
>
> No, it can't. Only an output port can also be declared as a reg.


Oops, thanks for letting me know.

> For an inout port, both sides must be nets.


Makes sense.

Paul.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
port sizes dont match ? dolly Verilog 1 10-29-2004 10:21 PM
please tell me why this inout port assignment isnt working!!! mw3382 Verilog 3 09-29-2004 05:29 PM
infer dual-port Block RAM with different dimensions kyrten Verilog 0 08-25-2004 07:55 PM
inout port in verilog Joy Chatterjee Verilog 2 06-16-2004 02:21 AM
port connection problem Rain Adelbert Verilog 3 04-02-2004 07:58 AM


All times are GMT +1. The time now is 12:30 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved