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  #1 (permalink)  
Old 11-26-2003, 07:48 PM
Robert Posey
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Default Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

Dear Gentle Persons,
Does anyone know where I could get a Verilog or VHDL RAM Model that models
common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram
Cells, Coupling faults Etc?

I would also be interested in Verilog or VHDL implementation of a March SS
RAM Test, or any March type RAM Test.

Robert Posey


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  #2 (permalink)  
Old 11-27-2003, 05:45 AM
pini
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Default Re: Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

check in actel's web site.
`timescale 1 ns/100 ps
// Behavioral description of FIFO with:
// active high write enable
// active high read enable
// active low asynchronous clear
// rising edge clock
// active high full flag
// active low empty flag

module reg_fifo (Data, Q, Aclr, Clock, WE, RE, FF, EF);

parameter width = 8;
parameter depth = 8;
parameter addr = 3;

input Clock, WE, RE, Aclr;
input [width-1:0] Data;
output FF, EF; //Full & Empty Flags
output [width-1:0] Q;
reg [width-1:0] Q;
reg [width-1:0] mem_data [depth-1:0];
reg [addr -1:0] WAddress, RAddress;
reg FF, EF;

// Write functional section
always @ (posedge Clock or negedge Aclr)
begin
if(!Aclr)
WAddress = #2 0;
else if(WE)
WAddress = #2 WAddress + 1;
end

// Write reg
always @ (posedge Clock)
begin
if(WE)
mem_data[WAddress] = Data;
end


// Read functional section
always @ (posedge Clock or negedge Aclr)
begin
if(!Aclr)
RAddress = #1 0;
else if (RE)
RAddress = #1 RAddress + 1;
end

// Read reg
always @ (posedge Clock)
begin
if(RE)
Q = mem_data[RAddress];
end

// Full Flag
always @ (posedge Clock or negedge Aclr)
begin
if(!Aclr)
FF = #1 1'b0;
else if
(
(WE & !RE) && //Write operation
( //Next cycle is full
(WAddress == RAddress-1) ||
( (WAddress == depth-1) && (RAddress == 1'b0) )
)
)
FF = #1 1'b1;
else
FF = #1 1'b0;
end

// Empty Flag
always @ (posedge Clock or negedge Aclr)
begin
if(!Aclr)
EF = #1 1'b0;
else if
(
(!WE & RE) && //Read operation
( //Next cycle is empty
(WAddress == RAddress+1) ||
( (RAddress == depth-1) && (WAddress == 1'b0) )
)
)
EF = #1 1'b0;
else
EF = #1 1'b1;
end

endmodule






"Robert Posey" <[email protected]> wrote in message news:<[email protected]_s51>...
> Dear Gentle Persons,
> Does anyone know where I could get a Verilog or VHDL RAM Model that models
> common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram
> Cells, Coupling faults Etc?
>
> I would also be interested in Verilog or VHDL implementation of a March SS
> RAM Test, or any March type RAM Test.
>
> Robert Posey

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  #3 (permalink)  
Old 12-03-2003, 09:35 PM
Andy Peters
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Posts: n/a
Default Re: Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

[email protected] (pini) wrote in message news:<[email protected] com>...
> check in actel's web site.
> `timescale 1 ns/100 ps
> // Behavioral description of FIFO with:


[snip[

> // Write functional section
> always @ (posedge Clock or negedge Aclr)
> begin
> if(!Aclr)
> WAddress = #2 0;
> else if(WE)
> WAddress = #2 WAddress + 1;
> end
>
> // Write reg
> always @ (posedge Clock)
> begin
> if(WE)
> mem_data[WAddress] = Data;
> end
>


[snip]

Yikes! Blocking assignments! Bad! Bad!

-a
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  #4 (permalink)  
Old 12-19-2003, 01:19 AM
Cliff Cummings
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Posts: n/a
Default Re: Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

[email protected] (Andy Peters) wrote in message news:<[email protected] com>...
> [email protected] (pini) wrote in message news:<[email protected] com>...
> > check in actel's web site.
> > `timescale 1 ns/100 ps
> > // Behavioral description of FIFO with:

>
> [snip[
>
> > // Write functional section
> > always @ (posedge Clock or negedge Aclr)
> > begin
> > if(!Aclr)
> > WAddress = #2 0;
> > else if(WE)
> > WAddress = #2 WAddress + 1;
> > end
> >
> > // Write reg
> > always @ (posedge Clock)
> > begin
> > if(WE)
> > mem_data[WAddress] = Data;
> > end
> >

>
> [snip]
>
> Yikes! Blocking assignments! Bad! Bad!
>
> -a


Even worse, blocking assignments with delays on the RHS! This does not
behave like real hardware. I just lost a lot of confidence in Actel!

If I could have taken RHS blocking delays out of the Verilog Standard,
I would have, but alas, too many engineers have used this abysmal
coding style in their fragile models.

Actel engineers should download a couple of my nonblocking assignment
papers from my web page www.sunburst-design.com/papers and maybe they
should contact me about some Advanced Verilog Training!

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
Verilog On-Site Training Sale - 4-day Courses for $1,200/Student
[email protected] / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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  #5 (permalink)  
Old 12-22-2003, 12:05 PM
Rudolf Usselmann
Guest
 
Posts: n/a
Default Re: Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

"Robert Posey" <[email protected]> wrote in message news:<[email protected]_s51>...
> Dear Gentle Persons,
> Does anyone know where I could get a Verilog or VHDL RAM Model that models
> common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram
> Cells, Coupling faults Etc?
>
> I would also be interested in Verilog or VHDL implementation of a March SS
> RAM Test, or any March type RAM Test.
>
> Robert Posey



You can download a free Verilog synthesizeable FIFO
and memories from OpenCores.

http://www.opencores.org/projects/generic_fifos/

The memories are in the "Dependencies" ...

Regards,
rudi
================================================== ======
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
...............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
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  #6 (permalink)  
Old 12-22-2003, 06:13 PM
Andy Peters
Guest
 
Posts: n/a
Default Re: Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.

[email protected] (Cliff Cummings) wrote in message news:<[email protected] om>...
> [email protected] (Andy Peters) wrote in message news:<[email protected] com>...
> > [email protected] (pini) wrote in message news:<[email protected] com>...
> > > check in actel's web site.
> > > `timescale 1 ns/100 ps
> > > // Behavioral description of FIFO with:

> >
> > [snip[
> >
> > > // Write functional section
> > > always @ (posedge Clock or negedge Aclr)
> > > begin
> > > if(!Aclr)
> > > WAddress = #2 0;
> > > else if(WE)
> > > WAddress = #2 WAddress + 1;
> > > end
> > >
> > > // Write reg
> > > always @ (posedge Clock)
> > > begin
> > > if(WE)
> > > mem_data[WAddress] = Data;
> > > end
> > >

> >
> > [snip]
> >
> > Yikes! Blocking assignments! Bad! Bad!
> >
> > -a

>
> Even worse, blocking assignments with delays on the RHS! This does not
> behave like real hardware. I just lost a lot of confidence in Actel!
>
> If I could have taken RHS blocking delays out of the Verilog Standard,
> I would have, but alas, too many engineers have used this abysmal
> coding style in their fragile models.
>
> Actel engineers should download a couple of my nonblocking assignment
> papers from my web page www.sunburst-design.com/papers and maybe they
> should contact me about some Advanced Verilog Training!


Actel isn't the only company guilty of this. For example, there are
some pretty yecchy memory models out there.

Methinks that the models are written by a company's most junior
engineers, and they're never checked by senior staff before being
released.

--a
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