FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-26-2007, 04:50 PM
Joe
Guest
 
Posts: n/a
Default LogicSim 3.1 Released!

Hi there,

I'd like to announce the release of LogicSim 3.1. This is a
maintenance and support release that addresses some outstanding issues
that were not addressed with 3.0 including some feature enhancements
and many bug fixes.

In this release, we have fixed some minor bugs and memory leaks. We
have also added some new features for the workspace, such as support
for creating sub-folders in the file navigator to improve navigation
for projects with many files. Please check out the release notes for
more info.

For existing customers, please receive your free upgrade here (http://
www.zeemz.com/maintenance.php), just enter your purchase time email
address and an activation key will be sent to you immediately. I'd
like to thank those who continue submitting bugs and feedbacks.
Without them, we would not be able to improve our software. Thanks for
being our valuable customers and users.

You can download LogicSim 3.1 here (http://www.zeemz.com/)
You can find this press release on our blog (http://www.zeemz.com/
blog/)

Joe,
Zeemz, Inc.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
LogicSim v3.0 Verilog Simulator is Here! Joe Verilog 0 06-13-2007 04:39 PM
Testers needed for LogicSim v2.0 (BETA) [email protected] Verilog 0 11-20-2006 05:41 PM
OpenSPARC released Pablo Bleyer Kocik Verilog 47 04-03-2006 06:03 PM
Confluence 0.10.3 Released tom Verilog 0 02-17-2005 10:19 PM
[ANN] Confluence 0.7.1 Released Tom Hawkins Verilog 0 10-23-2003 11:17 PM


All times are GMT +1. The time now is 03:44 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved