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Old 12-14-2005, 09:45 AM
SB
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Default log in Verilog parameter list

Hi all,

I am using parameters for the first time in Verilog.

I have two parameters A and B and I want one to be a function of the
other in the following way:

B = log2(A)

ie; I want B to be the logarithm to base 2 of A.

Is there any way I can do this in the Verilog parameter declaraton
list?

Any help would be great.

SB

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Old 12-15-2005, 07:26 PM
gabor
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Default Re: log in Verilog parameter list


SB wrote:
> Hi all,
>
> I am using parameters for the first time in Verilog.
>
> I have two parameters A and B and I want one to be a function of the
> other in the following way:
>
> B = log2(A)
>
> ie; I want B to be the logarithm to base 2 of A.
>
> Is there any way I can do this in the Verilog parameter declaraton
> list?
>
> Any help would be great.
>
> SB


I would normally approach this in the reverse order. That is I
would enter the value for B and have the definition of A look like
A = 1 << B, effectively A = 2^B. If in fact you can't enter B
because it comes from some external variable (which seems
unlikely for synthesize-time parameters) you may need to
code it using a search for the most significant 1 in A. There
were some recent threads on algorithms for this.

If you really want a non-integer log2(A) you may be out of luck.

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Old 12-15-2005, 10:03 PM
Guest
 
Posts: n/a
Default Re: log in Verilog parameter list


SB wrote:
> Hi all,
>
> I am using parameters for the first time in Verilog.
>
> I have two parameters A and B and I want one to be a function of the
> other in the following way:
>
> B = log2(A)
>
> ie; I want B to be the logarithm to base 2 of A.
>
> Is there any way I can do this in the Verilog parameter declaraton
> list?
>
> Any help would be great.
>
> SB


This works to give you the integer part:

// Number of channels, and the number of address bits to represent them
// 1< number_channels <= 128
parameter numch = number_channels;
parameter chaw = (number_channels <= 2) ? 1 :
(number_channels <= 4) ? 2 :
(number_channels <= 8) ? 3 :
(number_channels <= 16) ? 4 :
(number_channels <= 32) ? 5 :
(number_channels <= 64) ? 6 : 7;


Regards,

John McCaskill

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Old 12-16-2005, 06:49 PM
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Default Re: log in Verilog parameter list

As has already been pointed out, instead of passing the larger
parameter and trying to compute the smaller one with a log2, you can
pass the smaller parameter and compute the larger one from it with (1
<< N). Of course, this only works if the larger parameter is an exact
power of 2 (as it is in most cases, such as the size of a memory
addressable with a given number of address bits).

[email protected] wrote:
> parameter chaw = (number_channels <= 2) ? 1 :
> (number_channels <= 4) ? 2 :
> (number_channels <= 8) ? 3 :
> (number_channels <= 16) ? 4 :
> (number_channels <= 32) ? 5 :
> (number_channels <= 64) ? 6 : 7;


This approach works also. If you need this complex expression in
multiple places, you can define a parameterized log2 macro that expands
to the expression, and use that. This expression can be extended to
cover values up to 4 billion using 32 compares, which is somewhat bulky
but not unreasonable. This assumes that your tools support
parameterized macros (from Verilog-1995).

This can also be done with a Verilog-2001 constant function. But then
you have to write the log2 function correctly (I believe the one
published in the Verilog-2001 LRM was wrong), and include the
definition in any module where you want to use it.

The Verilog-2005 standard defines a $clog2 system function that
computes the log2 rounded up to the next highest integer, and which can
be used in constant expressions. However, you can't expect tools to be
supporting that yet.

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