[email protected] (DaveW) wrote in message news:<

[email protected] com>...

> I came up with the following (simplified) code snippet for a leading

> zero counter - question is: is this the "best" way to do it? I know it

> works but I wonder if there is a more efficient/correct approach.

> ==============================================

> :

> input clk;

> input [23:0] xn;

> :

> :

> reg [23:0] lz_count_reg;

> reg [4:0] count;

>

> always @( posedge clk )

> begin

> lz_count_reg=24;

> for( count=0; count<24; count=count+1 )

> if( xn[ count ] )

> lz_count_reg=23-count;

> end

> =================================================

>

> Thanks in anticipation...
You need to think with a HW hat on to get really good performance. Dig

up an old TI TTL book and check out the section on Priority Encoding.

Things have't changed much since then. The natural way to think is

recursive division. Typically for large N say 16 or 64 partition into

4 ways and solve that and recombine results. When you know how to

recombine, you only need to PE 4bits and build result from there.

Should be possible to do arbitrary encoder for N (power of 2 or 4) in

about O logN time where O might be 1 or 2 gate delays. In an ASIC, O

might be closer to transit time so even faster. For an

FPGA you will

be better off with adder type circuit and XST doesn't seem to synth

fast adders with ripple adder until the length is long enough say 4b,

so recursion doesn't work here. And doing math with multiple adder

fragments in one pipe will be slow too.

If your input word is all 0's but for a single 1, the solution is much

easier, then a tree decoder works quickly. If you have 1 or more 1s,

1st build a force all right 1s to 0 stage infront. This stage looks

triangular if you do it bitwise, but again recursion can help here

too, break into 4 or 8 bit sub words. The right most 1 or lsb needs to

be killed by all the 1's to the left, and big wide gates in

FPGA are

also slow.

Its a solved problem, but not neccesary encoded into any tool I know

of. Also look at the big blue Verilog/VHDL book by Smith IIRC that

describes hundreds of synth code modules in both langs with

schematics. PEs should be in there. its a must have book for any HW

guy.

johnjakson_usa_com