Hello,

I am new to verilog and saw that you had answered a question on a very

similar question I have. I have two bidi signals on my board. t_obs and

f_obs that are connected thru an active low quickswitch, obsiso. If obsiso

is low and they don't equal each other then t_obs and f_obs should be the

same. The problem I see with verilog is that they do not like a pin being

used like a reg and a wire. How do I get around this? Please look at my

example code.

I wrote this code following your example from this posting but it did not

work:

http://groups.google.com/groups?q=ho...rcn.net&rnum=1
inout t_obs; //bidi pin

inout f_obs; // bidi pin

input d_obsiso; // enables quick switch

tri1 f_obs;

tri1 t_obs;

wire d_obsiso;

assign t_obs = (!d_obsiso && (f_obs != t_obs)) ? f_obs :1'bz; // if obsiso

is low and f is not equal to t then t_obs = f_obs or else it is high z

always @(f_obs) //whenever f obs transitions

begin

if (d_obsiso == 0 && (f_obs != t_obs)) //same condtion as described

above (if quickswitch is low then f is not = to t then set

// them equal.

f_obs <= t_obs;

end

I tried this and it did not work because of the same bug.

`timescale 1ns/10ps

module OBS (f_obs, t_obs, d_obsiso);

inout f_obs;

inout t_obs;

input d_obsiso;

tri1 f_obs;

tri1 t_obs;

wire d_obsiso;

always @(t_obs) begin

if (d_obsiso == 0 && (f_obs != t_obs))

f_obs = t_obs; // does not like this-

else

t_obs = 1'bz;

end

always @(f_obs) begin

if (d_obsiso == 0 && (t_obs != f_obs))

t_obs = f_obs; // does not like this-

else

f_obs = 1'bz;

end

endmodule

Please help.