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  #1 (permalink)  
Old 04-04-2007, 09:31 PM
Verictor
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Default inferring a dual port memory

Hi,

I try to infer a dual port RAM after synthesis. DesignWare maybe a
good candidate doing this but I have never used it before. So if
someone who had applied it before can provide a very simple example
that would be very helpful.

My dual port RAM model is described in the following pseudo code
(detail skipped)

always @(posedge clock) begin : read
Temp_reg <= memory[address];
end

always @(negedge clock) begin: write
memory[address] <= Temp_reg;
end

Thanks

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  #2 (permalink)  
Old 04-04-2007, 10:25 PM
John_H
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Default Re: inferring a dual port memory

"Verictor" <[email protected]> wrote in message
news:[email protected] ups.com...
> Hi,
>
> I try to infer a dual port RAM after synthesis. DesignWare maybe a
> good candidate doing this but I have never used it before. So if
> someone who had applied it before can provide a very simple example
> that would be very helpful.
>
> My dual port RAM model is described in the following pseudo code
> (detail skipped)
>
> always @(posedge clock) begin : read
> Temp_reg <= memory[address];
> end
>
> always @(negedge clock) begin: write
> memory[address] <= Temp_reg;
> end
>
> Thanks


As long as the address is a registered value, synthesizers such as
SynplifyPro will infer the dual-port for an FPGA target.

If you're working with an ASIC target, it is very specific to your tool set
and target silicon as far as what infers, what doesn't, and how.


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  #3 (permalink)  
Old 04-05-2007, 04:16 PM
Verictor
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Posts: n/a
Default Re: inferring a dual port memory

On Apr 4, 3:25 pm, "John_H" <[email protected]> wrote:
> "Verictor" <[email protected]> wrote in message
>
> news:[email protected] ups.com...
>
>
>
> > Hi,

>
> > I try to infer a dual port RAM after synthesis. DesignWare maybe a
> > good candidate doing this but I have never used it before. So if
> > someone who had applied it before can provide a very simple example
> > that would be very helpful.

>
> > My dual port RAM model is described in the following pseudo code
> > (detail skipped)

>
> > always @(posedge clock) begin : read
> > Temp_reg <= memory[address];
> > end

>
> > always @(negedge clock) begin: write
> > memory[address] <= Temp_reg;
> > end

>
> > Thanks

>
> As long as the address is a registered value, synthesizers such as
> SynplifyPro will infer the dual-port for an FPGA target.
>
> If you're working with an ASIC target, it is very specific to your tool set
> and target silicon as far as what infers, what doesn't, and how.



Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

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  #4 (permalink)  
Old 04-05-2007, 05:06 PM
John_H
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Posts: n/a
Default Re: inferring a dual port memory

"Verictor" <[email protected]> wrote in message
news:[email protected] ups.com...
<snip>
> Right. I am working on an ASIC target. My tools are Physical Compiler
> and a 130nm process. I tried before I posted my question. It just
> didn't provide what I need. Can you tell me what to look at when it
> infers cells?
>
> Thanks a lot


I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this tool.
It may be that you need to have two versions of the address to get the
synthesis to recognize it as two ports rather than a malformed single port
memory; this was a problem for another poster recently. If you can't find
documentation, try the technical support you're already paying dearly for.


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  #5 (permalink)  
Old 04-05-2007, 05:48 PM
Mike Lewis
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Posts: n/a
Default Re: inferring a dual port memory


"John_H" <[email protected]> wrote in message
news:[email protected]
> "Verictor" <[email protected]> wrote in message
> news:[email protected] ups.com...
> <snip>
>> Right. I am working on an ASIC target. My tools are Physical Compiler
>> and a 130nm process. I tried before I posted my question. It just
>> didn't provide what I need. Can you tell me what to look at when it
>> infers cells?
>>
>> Thanks a lot

>
> I can't, perhaps someone else can.
>
> The Physical Compiler documentation may include specific documentation on
> inferring memories. It's important enough in my FPGA work that the
> synthesis tools I work with have several pages dedicated to memory
> inference. It may be that you need to instantiate dual ports in this
> tool. It may be that you need to have two versions of the address to get
> the synthesis to recognize it as two ports rather than a malformed single
> port memory; this was a problem for another poster recently. If you can't
> find documentation, try the technical support you're already paying dearly
> for.
>


In the ASIC world you have to instantiate the specific memory block that you
want to use. The sysnthesizer won't infer a memory ... it will just create
FFs.

Mike


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  #6 (permalink)  
Old 04-05-2007, 07:03 PM
Verictor
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Posts: n/a
Default Re: inferring a dual port memory

On Apr 5, 10:48 am, "Mike Lewis" <[email protected]> wrote:
> "John_H" <[email protected]> wrote in message
>
> news:[email protected]
>
>
>
>
>
> > "Verictor" <[email protected]> wrote in message
> >news:[email protected] oups.com...
> > <snip>
> >> Right. I am working on an ASIC target. My tools are Physical Compiler
> >> and a 130nm process. I tried before I posted my question. It just
> >> didn't provide what I need. Can you tell me what to look at when it
> >> infers cells?

>
> >> Thanks a lot

>
> > I can't, perhaps someone else can.

>
> > The Physical Compiler documentation may include specific documentation on
> > inferring memories. It's important enough in my FPGA work that the
> > synthesis tools I work with have several pages dedicated to memory
> > inference. It may be that you need to instantiate dual ports in this
> > tool. It may be that you need to have two versions of the address to get
> > the synthesis to recognize it as two ports rather than a malformed single
> > port memory; this was a problem for another poster recently. If you can't
> > find documentation, try the technical support you're already paying dearly
> > for.

>
> In the ASIC world you have to instantiate the specific memory block that you
> want to use. The sysnthesizer won't infer a memory ... it will just create
> FFs.
>
> Mike- Hide quoted text -
>
> - Show quoted text -


Thanks for the comment. Doesn't the DesignWare is coming in to do the
inferring job?

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  #7 (permalink)  
Old 04-08-2007, 10:14 AM
rjain
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Posts: n/a
Default Re: inferring a dual port memory

On Apr 5, 11:03 pm, "Verictor" <[email protected]> wrote:
> On Apr 5, 10:48 am, "Mike Lewis" <[email protected]> wrote:
>
>
>
> > "John_H" <[email protected]> wrote in message

>
> >news:[email protected]

>
> > > "Verictor" <[email protected]> wrote in message
> > >news:[email protected] oups.com...
> > > <snip>
> > >> Right. I am working on an ASIC target. My tools are Physical Compiler
> > >> and a 130nm process. I tried before I posted my question. It just
> > >> didn't provide what I need. Can you tell me what to look at when it
> > >> infers cells?

>
> > >> Thanks a lot

>
> > > I can't, perhaps someone else can.

>
> > > The Physical Compiler documentation may include specific documentation on
> > > inferring memories. It's important enough in my FPGA work that the
> > > synthesis tools I work with have several pages dedicated to memory
> > > inference. It may be that you need to instantiate dual ports in this
> > > tool. It may be that you need to have two versions of the address to get
> > > the synthesis to recognize it as two ports rather than a malformed single
> > > port memory; this was a problem for another poster recently. If you can't
> > > find documentation, try the technical support you're already paying dearly
> > > for.

>
> > In the ASIC world you have to instantiate the specific memory block that you
> > want to use. The sysnthesizer won't infer a memory ... it will just create
> > FFs.

>
> > Mike- Hide quoted text -

>
> > - Show quoted text -

>
> Thanks for the comment. Doesn't the DesignWare is coming in to do the
> inferring job?


For asic design, for memories, generally memory compilers from third
party vendors like artisan/virage etc are used to generate simulation
model/synthesis model/layout hard macro, and instantiated directly
instead of synthesis tool inferring it...
If you allow synthesis tool, it will always implement it using regular
flops with a big area/power penality. By using memories from other
vendors, you have many options like latch based, high density flop
based, true SRAM etc...
I don't think designware compiles memories...

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  #8 (permalink)  
Old 04-08-2007, 06:59 PM
Verictor
Guest
 
Posts: n/a
Default Re: inferring a dual port memory

On Apr 8, 3:14 am, "rjain" <[email protected]> wrote:
> On Apr 5, 11:03 pm, "Verictor" <[email protected]> wrote:
>
>
>
>
>
> > On Apr 5, 10:48 am, "Mike Lewis" <[email protected]> wrote:

>
> > > "John_H" <[email protected]> wrote in message

>
> > >news:[email protected]

>
> > > > "Verictor" <[email protected]> wrote in message
> > > >news:[email protected] oups.com...
> > > > <snip>
> > > >> Right. I am working on an ASIC target. My tools are Physical Compiler
> > > >> and a 130nm process. I tried before I posted my question. It just
> > > >> didn't provide what I need. Can you tell me what to look at when it
> > > >> infers cells?

>
> > > >> Thanks a lot

>
> > > > I can't, perhaps someone else can.

>
> > > > The Physical Compiler documentation may include specific documentation on
> > > > inferring memories. It's important enough in my FPGA work that the
> > > > synthesis tools I work with have several pages dedicated to memory
> > > > inference. It may be that you need to instantiate dual ports in this
> > > > tool. It may be that you need to have two versions of the address to get
> > > > the synthesis to recognize it as two ports rather than a malformed single
> > > > port memory; this was a problem for another poster recently. If you can't
> > > > find documentation, try the technical support you're already paying dearly
> > > > for.

>
> > > In the ASIC world you have to instantiate the specific memory block that you
> > > want to use. The sysnthesizer won't infer a memory ... it will just create
> > > FFs.

>
> > > Mike- Hide quoted text -

>
> > > - Show quoted text -

>
> > Thanks for the comment. Doesn't the DesignWare is coming in to do the
> > inferring job?

>
> For asic design, for memories, generally memory compilers from third
> party vendors like artisan/virage etc are used to generate simulation
> model/synthesis model/layout hard macro, and instantiated directly
> instead of synthesis tool inferring it...
> If you allow synthesis tool, it will always implement it using regular
> flops with a big area/power penality. By using memories from other
> vendors, you have many options like latch based, high density flop
> based, true SRAM etc...
> I don't think designware compiles memories...- Hide quoted text -
>
> - Show quoted text -


This is new to me. Do you have relevant documentation how to
instantiate the models?

Thanks

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