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Old 11-25-2004, 04:54 AM
maTheMatic
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Default Illegal reference to net

HI,all
I am learning verilog. The following codes can't be compiled with
the error information "Illegal reference to net "out"" under the
Modelsim SE.

module connect(
input wire in,
output wire out
);

always
begin
#3 out <= in;
end
endmodule

Why can't I direct assign (or connect directly) the input wire to the
output wire? When I change the type of out from wire to reg,then every
thing is ok. Yes, I know the reg can't be assigned with wire type's
things, but how about wire to wire?what is the basic laws behind the
assignment?

Regards

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  #2 (permalink)  
Old 11-25-2004, 09:01 AM
Pooja Maheshwari
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Default Re: Illegal reference to net

Its simple.
Inside always block, you can only assign to reg or variables not nets.
With assign statement, you can assign nets.
In both type of assignments, you can have either wire or reg on RHS.

- Pooja

maTheMatic wrote:

> HI,all
> I am learning verilog. The following codes can't be compiled with
> the error information "Illegal reference to net "out"" under the
> Modelsim SE.
>
> module connect(
> input wire in,
> output wire out
> );
>
> always
> begin
> #3 out <= in;
> end
> endmodule
>
> Why can't I direct assign (or connect directly) the input wire to the
> output wire? When I change the type of out from wire to reg,then every
> thing is ok. Yes, I know the reg can't be assigned with wire type's
> things, but how about wire to wire?what is the basic laws behind the
> assignment?
>
> Regards


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  #3 (permalink)  
Old 11-25-2004, 10:30 AM
Neo
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Posts: n/a
Default Re: Illegal reference to net

"maTheMatic" <[email protected]> wrote in message news:<[email protected] roups.com>...
> HI,all
> I am learning verilog. The following codes can't be compiled with
> the error information "Illegal reference to net "out"" under the
> Modelsim SE.
>
> module connect(
> input wire in,
> output wire out
> );
>
> always
> begin
> #3 out <= in;
> end
> endmodule


The rule is you cant assign to a wire inside an always block.
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  #4 (permalink)  
Old 11-26-2004, 03:16 AM
maTheMatic
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Default Re: Illegal reference to net

what is the consideration behind the above rule? or where can I find
the reference? thx for both of above guys!

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  #5 (permalink)  
Old 11-28-2004, 05:04 PM
Swapnajit Mittra
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Default Re: Illegal reference to net

"maTheMatic" <[email protected]> wrote in message news:<[email protected] roups.com>...
> what is the consideration behind the above rule? or where can I find
> the reference? thx for both of above guys!


Some people will say that a 'wire' type in Verilog
is supposed to be something akin to a physical
wire - that carries a signal but can not store
a value. You will have to use a 'reg' type to do
that.

But, more simply speaking, Verilog being a programming
language, just as all languages, you need to abide by
some rules and regulations. In this case, it is 'a wire
type variable can not be a valid L-value of a procedural
assignment statement'.

Official Verilog Language Reference Manual (IEEE Std.
1364-2001) can be purchased from IEEE store at

http://standards.ieee.org

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